Currently, only the first matched node will be handled. This leads
to jtag switching broken for RK3576, as rk3576-sys-grf is found before
rk3576-ioc-grf. Change the code to scan all the possible node to fix
the problem.
Fixes: e1aaecacfa ("soc: rockchip: grf: Add rk3576 default GRF values")
Cc: stable@vger.kernel.org
Cc: Detlev Casanova <detlev.casanova@collabora.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Tested-by: Marco Schirrmeister <mschirrmeister@gmail.com>
Link: https://patch.msgid.link/1768524932-163929-3-git-send-email-shawn.lin@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Similar to the RK3288, the RK3368 has two different implementations of
the PWM block inside the SoC - the newer ones that we have a driver for
and that is used on every SoC and a previous variant that was likely
left as a fallback if the new one creates problems.
The devicetree is already set up for the new variant, so make sure
we actually use it - similar to the RK3288.
Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
Link: https://patch.msgid.link/20251021074254.87065-4-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
drivers that use constant masks.
Switch the rockchip grf driver to the FIELD_PREP_WM16_CONST macro, which
brings with it more error checking while still being able to be used in
initializers.
All HIWORD_UPDATE instances and its definition are removed from the
driver, as the conversion here is obvious, and static_asserts were used
during development to make sure the ones greater than one bit in width
were really equivalent.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Yury Norov (NVIDIA) <yury.norov@gmail.com>
Set SW controlled i3c weak pull up and disable JTAG function on SDMMC IO.
The i3c weak pull up is activated to let all gpio banks be controlled
by the pinctrl driver.
Disabling the JTAG function lets the SDMMC core use its full IO width.
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Acked-by: Dragan Simic <dsimic@manjaro.org>
Link: https://lore.kernel.org/r/20240822195706.920567-3-detlev.casanova@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
RK3128 has a setting in GRF which selects whether the vpu attached iommu
uses the AXI clock of the decoder (vdpu) or the encoder (vepu). The
default is vepu but some part of the vendor firmware sets it to vdpu.
In order to be independent on whether any of those vendor firmware blobs is
used to boot the SoC reset "vpu main clock" setting to it's default value.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20240523185633.71355-3-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
These are all minor cleanups for platform specific code in arch/arm/
and some of the associated drivers. The majority of these are work
done by Rob Herring to improve the way devicetreee header files
are handled.
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Merge tag 'soc-arm-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC cleanups from Arnd Bergmann:
"These are all minor cleanups for platform specific code in arch/arm/
and some of the associated drivers. The majority of these are work
done by Rob Herring to improve the way devicetreee header files are
handled"
* tag 'soc-arm-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (49 commits)
ARM: davinci: Drop unused includes
ARM: s5pv210: Explicitly include correct DT includes
ARM: dove: Drop unused includes
ARM: mvebu: Explicitly include correct DT includes
Documentation/process: maintainer-soc: document dtbs_check requirement for Samsung
MAINTAINER: samsung: document dtbs_check requirement for Samsung
Documentation/process: maintainer-soc: add clean platforms profile
MAINTAINERS: soc: reference maintainer profile
ARM: nspire: Remove unused header file mmio.h
ARM: nspire: Use syscon-reboot to handle restart
soc: fsl: Explicitly include correct DT includes
soc: xilinx: Explicitly include correct DT includes
soc: sunxi: Explicitly include correct DT includes
soc: rockchip: Explicitly include correct DT includes
soc: mediatek: Explicitly include correct DT includes
soc: aspeed: Explicitly include correct DT includes
firmware: Explicitly include correct DT includes
bus: Explicitly include correct DT includes
ARM: spear: Explicitly include correct DT includes
ARM: mvebu: Explicitly include correct DT includes
...
RK3588 has the same issue as other earlier RK SoCs. JTAG
functionality muxed to some SDMMC data pins causes issues with SDMMC
interface. Without this patch, I can only use SDMMC inteface
with bus-width = <1>. (JTAG is muxed to data pins D2 and D3)
Signed-off-by: Ondrej Jirman <megi@xff.cz>
Link: https://lore.kernel.org/r/20230619011002.2249960-1-megi@xff.cz
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it as merged into the regular platform bus.
As part of that merge prepping Arm DT support 13 years ago, they
"temporarily" include each other. They also include platform_device.h
and of.h. As a result, there's a pretty much random mix of those include
files used throughout the tree. In order to detangle these headers and
replace the implicit includes with struct declarations, users need to
explicitly include the correct includes.
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230803-dt-header-cleanups-for-soc-v2-20-d8de2cc88bff@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
of_find_matching_node_and_match returns a node pointer with refcount
incremented, we should use of_node_put() on it when done.
Add missing of_node_put() to avoid refcount leak.
Fixes: 4c58063d42 ("soc: rockchip: add driver handling grf setup")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Link: https://lore.kernel.org/r/20220516072013.19731-1-linmq006@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The rk3566 dwc3 otg port clock is unavailable at boot, as it defaults to
the combophy as the clock source. As combophy0 doesn't exist on rk3566,
we need to set the clock source to the usb2 phy instead.
Add handling to the grf driver to handle this on boot.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Link: https://lore.kernel.org/r/20220408151237.3165046-3-pgwipeout@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Based on 2 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation #
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 4122 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Enrico Weigelt <info@metux.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The rk3288 SoC has two PWM implementations available, the "old"
implementation and the "new" one. You can switch between the two of
them by flipping a bit in the grf.
The "old" implementation is the default at chip power up but isn't the
one that's officially supposed to be used. ...and, in fact, the
driver that gets selected in Linux using the rk3288 device tree only
supports the "new" implementation.
Long ago I tried to get a switch to the right IP block landed in the
PWM driver (search for "rk3288: Switch to use the proper PWM IP") but
that got rejected. In the mean time the grf has grown a full-fledged
driver that already sets other random bits like this. That means we
can now get the fix landed.
For those wondering how things could have possibly worked for the last
4.5 years, folks have mostly been relying on the bootloader to set
this bit. ...but occasionally folks have pointed back to my old patch
series [1] in downstream kernels.
[1] https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1391597.html
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Disable IO function switching between sdmmc and jtag
for RK3128 SoCs.
Signed-off-by: Xiao Yao <xiaoyao@rock-chips.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Disable IO function switching between sdmmc and jtag
for RK3228 and RK3229 SoCs.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Disable IO function switching between sdmmc and jtag
for RK3328 Soc.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The General Register Files are an area of registers containing a lot
of single-bit settings for numerous components as well full components
like usbphy control. Therefore all used components are accessed
via the syscon provided by the grf nodes or from the sub-devices
created through the simple-mfd created from the grf node.
Some settings are not used by anything but will need to be set up
according to expectations on the kernel side.
Best example is the force_jtag setting, which defaults to on and
results in the soc switching the pin-outputs between jtag and sdmmc
automatically depending on the card-detect status. This conflicts
heavily with how the dw_mmc driver expects to do its work and also
with the clock-controller, which has most likely deactivated the
jtag clock due to it being unused.
So far the handling of this setting was living in the mach-rockchip
code for the arm32-based rk3288 but that of course doesn't work
for arm64 socs and would also look ugly for further arm32 socs.
Also always disabling this setting is quite specific to linux and
its subsystems, other operating systems might prefer other settings,
so that the bootloader cannot really set a sane default for all.
So introduce a top-level driver for the grf that handles these
settings that need to be a certain way but nobody cares about.
Other needed settings might surface in the future and can then
be added here, but only as a last option. Ideally general GRF
settings should be handled in the driver needing them.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
