Enable the Kaanapali display, video, camera and gpu clock controller
for their respective functionalities on the Qualcomm Kaanapali QRD and
MTP boards.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260224-knp-dts-misc-v6-10-79d20dab8a60@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Enable the interconnect, pinctrl and Global Clock Controller (GCC)
providers as built-in, and the Top Control and Status Register (TCSR)
clock provider as module, on the Qualcomm Eliza SoC.
These are all necessary in order to be able to boot up Eliza-based MTP
board with debug UART and rootfs on UFS storage.
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260316-arm64-defconfig-enable-eliza-basic-providers-v1-1-7ae581670aa8@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Enable the S5KJN1 driver which is used for the front camera on the
Fairphone 5 smartphone.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260313-fp5-s5kjn1-v1-3-fa4f1c727318@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Microchip is the only platform that doesn't have a top-level switch for
disabling all SoC families. Align it with other platforms and update the
arm64 defconfig to keep the default config the same.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260226143615.65788-1-bartosz.golaszewski@oss.qualcomm.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Enable the configurations needed for Aquila AM69 SoM and compatible
carrier boards.
- CONFIG_SENSORS_AMC6821, needed for the fan controller on the clover
and dev carrier board (as module).
- CONFIG_POWER_RESET_GPIO and CONFIG_POWER_RESET_GPIO_RESTART needed
for poweroff and restart functionalities (as built-in, it's not
possible to set them as 'm').
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Link: https://patch.msgid.link/20260306153130.102972-1-francesco@dolcini.it
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Enable the Qualcomm WCD937x headphone audio codec as a loadable module,
as it is now required on the QCM6490 IDP platform.
Signed-off-by: Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260121102606.1753970-1-ajay.nandam@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
All Qualcomm SoCs starting from SM8650 provide access to the Qualcomm
Trusted Execution Environment (QTEE) through the SMCInvoke interface,
implemented by the QCOMTEE driver. QTEE runs in the Secure World domain
on ARM64 CPUs and exposes secure services to Linux running in the Normal
World domain.
This change enables the QCOMTEE driver as a module to support
communication with QTEE.
QCOMTEE has been tested on a Qualcomm RB3Gen2 board by loading and
executing a Trusted Application via tests hosted at
github.com/qualcomm/minkipc.
Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Reviewed-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Tested-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260114-qcom_qcomtee_defconfig-v4-1-ec676311171f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Enable pinctrl, clocks and interconnect drivers as built-in
in order for serial console to be available before kernel
reaches "init" on Qualcomm Glymur CRD.
Additionally, booting rootfs from NVMe requires TCSRCC to
be enabled as module
Enable dispcc as module which is a dependency for display enablement
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260219-upstream_v3_glymur_introduction-v8-2-8ce4e489ebb6@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Enable the SM8750 video, camera and gpu clock controller for their
respective functionalities on the Qualcomm SM8750 MTP boards.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260220-sm8750_defconfig_cc-v1-1-666aa922b392@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
These are the usual updates, enabling mode newly merged device drivers for
various Arm and RISC-V based platforms in the defconfig files. The Renesas
and NXP defconfig files also get a refresh for modified Kconfig options.
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Merge tag 'soc-defconfig-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC defconfig updates from Arnd Bergmann:
"These are the usual updates, enabling mode newly merged device drivers
for various Arm and RISC-V based platforms in the defconfig files.
The Renesas and NXP defconfig files also get a refresh for modified
Kconfig options"
* tag 'soc-defconfig-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
riscv: defconfig: spacemit: k3: enable clock support
ARM: defconfig: turn off CONFIG_EXPERT
ARM: defconfig: move entries
arm64: defconfig: Enable configurations for Kontron SMARC-sAM67
ARM: imx_v4_v5_defconfig: update for v6.19-rc1
arm64: defconfig: Enable Apple Silicon drivers
arm64: select APPLE_PMGR_PWRSTATE for ARCH_APPLE
arm64: defconfig: Enable Mediatek HDMIv2 driver
ARM: shmobile: defconfig: Refresh for v6.19-rc1
arm64: defconfig: Enable PCIe for the Renesas RZ/G3S SoC
arm64: defconfig: Enable RZ/G3E USB3 PHY driver
arm64: defconfig: Enable EC drivers for Qualcomm-based laptops
arm64: defconfig: Enable options for Qualcomm Milos SoC
ARM: imx_v6_v7_defconfig: enable EPD regulator needed for Kobo Clara 2e
ARM: imx_v6_v7_defconfig: Configure CONFIG_SND_SOC_FSL_ASOC_CARD as module
ARM: multi_v7_defconfig: enable DA9052 and MC13XXX
arm64: defconfig: enable clocks, interconnect and pinctrl for Qualcomm Kaanapali
arm64: defconfig: Drop duplicate CONFIG_OMAP_USB2 entry
arm64: defconfig: Enable missing AMD/Xilinx drivers
This adds a single change, enabling to compile the
MediaTek HDMIv2 driver as module.
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Merge tag 'mtk-defconfig-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/defconfig
MediaTek defconfig updates
This adds a single change, enabling to compile the
MediaTek HDMIv2 driver as module.
* tag 'mtk-defconfig-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux:
arm64: defconfig: Enable Mediatek HDMIv2 driver
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Enable most drivers required for Apple Silicon as module inside
defconfig
- Enable the power-domain driver when ARCH_APPLE and PM is selected
since it's critical for booting these systems
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Merge tag 'apple-soc-defconfig-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux into soc/defconfig
Apple SoC defconfig update for 6.20
- Enable most drivers required for Apple Silicon as module inside
defconfig
- Enable the power-domain driver when ARCH_APPLE and PM is selected
since it's critical for booting these systems
* tag 'apple-soc-defconfig-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux:
arm64: defconfig: Enable Apple Silicon drivers
arm64: select APPLE_PMGR_PWRSTATE for ARCH_APPLE
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Qualcomm SC7280 and SM8350 SoCs have slightly different LPASS audio
blocks (v9.4.5 and v9.2), however the LPASS LPI pin controllers are
exactly the same. The driver for SM8350 has two issues, which can be
fixed by simply moving over to SC7280 driver which has them correct:
1. "i2s2_data_groups" listed twice GPIO12, but should have both GPIO12
and GPIO13,
2. "swr_tx_data_groups" contained GPIO5 for "swr_tx_data2" function, but
that function is also available on GPIO14, thus listing it twice is
not necessary. OTOH, GPIO5 has also "swr_rx_data1", so selecting
swr_rx_data function should not block the TX one.
Fixes: be9f6d5638 ("pinctrl: qcom: sm8350-lpass-lpi: add SM8350 LPASS TLMM")
Cc: stable@vger.kernel.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
Enable drivers for hardware present on Apple Silicon machines. None of
these drivers are critical so build them as modules. The reset and RTC
macsmc drivers would be useful as built-in drivers but they have large
dependencies so keep them as modules.
The size increases are minor and are offsetted by already merged
"default ARCH_APPLE" removals from the linked original submission.
vmlinux 157782640 -> 157902032 (+119392)
Image 41007616 -> 41073152 (+ 65536)
Link: https://lore.kernel.org/asahi/20250612-apple-kconfig-defconfig-v1-0-0e6f9cb512c1@kernel.org/
Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20251231-arch-arm64-apple-defconfig-v1-2-4ff19805ba39@jannau.net
Signed-off-by: Sven Peter <sven@kernel.org>
In order to enable the HDMI output support on Mediatek Genio 510-EVK,
700-EVK, and 1200-EVK boards, enable the driver for it in the default
configuration.
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Enable the pinctrl, clock and interconnect drivers for the Qualcomm
Milos SoC. This is required for booting The Fairphone (Gen. 6).
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251219-milos-defconfig-v1-1-f58012ac8ef6@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Enable necessary drivers for booting Qualcomm Kaanapali QRD and MTP
boards. The serial engine must be properly setup before kernel reach
"init", so UART driver and its dependencies needs to be built in, enable
its dependency GCC, interconnect and pinctrl as built-in meanwhile enable
TCSRCC as module.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251215-knp-dts-v4-2-1541bebeb89f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
CONFIG_OMAP_USB2 is already enabled as a module in the default defconfig
since commit 8a703a728a ("arm64: defconfig: Enable USB2 PHY Driver").
Remove the duplicate entry to fix the following warning:
arch/arm64/configs/defconfig:1705:warning: override: reassigning to symbol OMAP_USB2
Fixes: 91fe3315cdf9f ("arm64: defconfig: Enable missing AMD/Xilinx drivers")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20251015150728.118296-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Over years number of upstream drivers have grown for AMD/Xilinx SOCs
(ZynqMP, Versal, Versal NET) but they are not enabled by default in
defconfig that's why enable all drivers for these SOCs including USB5744
on board USB hub available on Kria ZynqMP based SOMs and Carrier Cards.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/457c3a128e300241afd20da693d1d80a35d1ece6.1758099050.git.michal.simek@amd.com
These three new families of SoC are split out into a separate branch
because they touch multiple parts of the source tree and are better
left separate for the initial merge.
- Black Sesame Technologies C1200 is an automotive SoC using
Cortex-A78 CPU cores
- Anlogic dr1v90 (not to be confused with Amlogic) is an FPGA
platform using a single nuclei ux900 RISC-V core
- Tenstorrent Blackhole is a Neural Processing Unit using
custom "Tensix" cores for computation offload managed by
Linux running on SiFive X280 RISC-V cores.
Support for all three is rather rudimentary at the moment and will get
improved as device drivers are merged through other tree.
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Merge tag 'soc-newsoc-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull new SoC families update from Arnd Bergmann:
"These three new families of SoC are split out into a separate branch
because they touch multiple parts of the source tree and are better
left separate for the initial merge.
- Black Sesame Technologies C1200 is an automotive SoC using
Cortex-A78 CPU cores
- Anlogic dr1v90 (not to be confused with Amlogic) is an FPGA
platform using a single nuclei ux900 RISC-V core
- Tenstorrent Blackhole is a Neural Processing Unit using custom
"Tensix" cores for computation offload managed by Linux running on
SiFive X280 RISC-V cores.
Support for all three is rather rudimentary at the moment and will get
improved as device drivers are merged through other tree"
* tag 'soc-newsoc-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (24 commits)
MAINTAINERS: add Black Sesame Technologies (BST) ARM SoC support
arm64: defconfig: enable BST platform support
arm64: dts: bst: add support for Black Sesame Technologies C1200 CDCU1.0 board
arm64: Kconfig: add ARCH_BST for Black Sesame Technologies SoCs
dt-bindings: arm: add Black Sesame Technologies (bst) SoC
dt-bindings: vendor-prefixes: Add Black Sesame Technologies Co., Ltd.
MAINTAINERS: Setup support for Anlogic tree
riscv: defconfig: Enable Anlogic SoC
riscv: dts: anlogic: Add Milianke MLKPAI FS01 board
riscv: dts: Add initial Anlogic DR1V90 SoC device tree
riscv: Add Anlogic SoC famly Kconfig support
dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart
dt-bindings: timer: Add Anlogic DR1V90 ACLINT MTIMER
dt-bindings: riscv: Add Anlogic DR1V90
dt-bindings: riscv: Add Nuclei UX900 compatibles
dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei
riscv: defconfig: Enable Tenstorrent SoCs
riscv: Kconfig.socs: Add ARCH_TENSTORRENT for Tenstorrent SoCs
riscv: dts: Add Tenstorrent Blackhole SoC PCIe cards
dt-bindings: interrupt-controller: Add Tenstorrent Blackhole compatible
...
As usual, a number of newly added drivers get enabled in the arm64 defconfig,
in addition to minor housekeeping work on defconfig files for arm32, arm64 and
riscv.
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Merge tag 'soc-defconfig-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC defconfig updates from Arnd Bergmann:
"As usual, a number of newly added drivers get enabled in the arm64
defconfig, in addition to minor housekeeping work on defconfig files
for arm32, arm64 and riscv"
* tag 'soc-defconfig-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (24 commits)
arm64: defconfig: enable Exynos ACPM clocks
arm64: defconfig: Remove the redundant SCHED_MC/SCHED_SMT
ARM: multi_v7_defconfig: Enable TI PRU Ethernet driver
arm64: defconfig: enable i.MX AIPSTZ driver
ARM: mxs_defconfig: enable sound drivers for imx28-amarula-rmm
arm64: defconfig: Enable i.MX95 drivers for pinctrl, Ethernet and PCIe
arm64: defconfig: enable rockchip camera interface
ARM: tegra: Enable EXT4 for Tegra
arm64: defconfig: Enable NVIDIA VRS PSEQ RTC
arm64: defconfig: Enable SX150x GPIO expander driver
riscv: defconfig: enable SPI_FSL_QUADSPI as a module
ARM: at91: at91_dt_defconfig: set MMC_SPI to module
arm64: defconfig: Build NSS clock controller driver for IPQ5424
arm64: defconfig: Enable SCSI UFS Crypto and Block Inline encryption drivers
arm64: defconfig: Add M31 eUSB2 PHY config
arm64: defconfig: Enable configs for Fairphone 3, 4, 5 smartphones
arm64: defconfig: Enable two Novatek display panels for MTP8750 and Tianma
arm64: defconfig: Enable RZ/T2H / RZ/N2H ADC driver
ARM: shmobile: defconfig: Refresh for v6.18-rc1
arm64: defconfig: Enable DW HDMI QP CEC support
...
API:
- Rewrite memcpy_sglist from scratch.
- Add on-stack AEAD request allocation.
- Fix partial block processing in ahash.
Algorithms:
- Remove ansi_cprng.
- Remove tcrypt tests for poly1305.
- Fix EINPROGRESS processing in authenc.
- Fix double-free in zstd.
Drivers:
- Use drbg ctr helper when reseeding xilinx-trng.
- Add support for PCI device 0x115A to ccp.
- Add support of paes in caam.
- Add support for aes-xts in dthev2.
Others:
- Use likely in rhashtable lookup.
- Fix lockdep false-positive in padata by removing a helper.
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Merge tag 'v6.19-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
Pull crypto updates from Herbert Xu:
"API:
- Rewrite memcpy_sglist from scratch
- Add on-stack AEAD request allocation
- Fix partial block processing in ahash
Algorithms:
- Remove ansi_cprng
- Remove tcrypt tests for poly1305
- Fix EINPROGRESS processing in authenc
- Fix double-free in zstd
Drivers:
- Use drbg ctr helper when reseeding xilinx-trng
- Add support for PCI device 0x115A to ccp
- Add support of paes in caam
- Add support for aes-xts in dthev2
Others:
- Use likely in rhashtable lookup
- Fix lockdep false-positive in padata by removing a helper"
* tag 'v6.19-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (71 commits)
crypto: zstd - fix double-free in per-CPU stream cleanup
crypto: ahash - Zero positive err value in ahash_update_finish
crypto: ahash - Fix crypto_ahash_import with partial block data
crypto: lib/mpi - use min() instead of min_t()
crypto: ccp - use min() instead of min_t()
hwrng: core - use min3() instead of nested min_t()
crypto: aesni - ctr_crypt() use min() instead of min_t()
crypto: drbg - Delete unused ctx from struct sdesc
crypto: testmgr - Add missing DES weak and semi-weak key tests
Revert "crypto: scatterwalk - Move skcipher walk and use it for memcpy_sglist"
crypto: scatterwalk - Fix memcpy_sglist() to always succeed
crypto: iaa - Request to add Kanchana P Sridhar to Maintainers.
crypto: tcrypt - Remove unused poly1305 support
crypto: ansi_cprng - Remove unused ansi_cprng algorithm
crypto: asymmetric_keys - fix uninitialized pointers with free attribute
KEYS: Avoid -Wflex-array-member-not-at-end warning
crypto: ccree - Correctly handle return of sg_nents_for_len
crypto: starfive - Correctly handle return of sg_nents_for_len
crypto: iaa - Fix incorrect return value in save_iaa_wq()
crypto: zstd - Remove unnecessary size_t cast
...
This is the main crypto library pull request for 6.19. It includes:
- Add SHA-3 support to lib/crypto/, including support for both the
hash functions and the extendable-output functions. Reimplement the
existing SHA-3 crypto_shash support on top of the library.
This is motivated mainly by the upcoming support for the ML-DSA
signature algorithm, which needs the SHAKE128 and SHAKE256
functions. But even on its own it's a useful cleanup.
This also fixes the longstanding issue where the
architecture-optimized SHA-3 code was disabled by default.
- Add BLAKE2b support to lib/crypto/, and reimplement the existing
BLAKE2b crypto_shash support on top of the library.
This is motivated mainly by btrfs, which supports BLAKE2b checksums.
With this change, all btrfs checksum algorithms now have library
APIs. btrfs is planned to start just using the library directly.
This refactor also improves consistency between the BLAKE2b code and
BLAKE2s code. And as usual, it also fixes the issue where the
architecture-optimized BLAKE2b code was disabled by default.
- Add POLYVAL support to lib/crypto/, replacing the existing POLYVAL
support in crypto_shash. Reimplement HCTR2 on top of the library.
This simplifies the code and improves HCTR2 performance. As usual,
it also makes the architecture-optimized code be enabled by default.
The generic implementation of POLYVAL is greatly improved as well.
- Clean up the BLAKE2s code.
- Add FIPS self-tests for SHA-1, SHA-2, and SHA-3.
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Merge tag 'libcrypto-updates-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ebiggers/linux
Pull crypto library updates from Eric Biggers:
"This is the main crypto library pull request for 6.19. It includes:
- Add SHA-3 support to lib/crypto/, including support for both the
hash functions and the extendable-output functions. Reimplement the
existing SHA-3 crypto_shash support on top of the library.
This is motivated mainly by the upcoming support for the ML-DSA
signature algorithm, which needs the SHAKE128 and SHAKE256
functions. But even on its own it's a useful cleanup.
This also fixes the longstanding issue where the
architecture-optimized SHA-3 code was disabled by default.
- Add BLAKE2b support to lib/crypto/, and reimplement the existing
BLAKE2b crypto_shash support on top of the library.
This is motivated mainly by btrfs, which supports BLAKE2b
checksums. With this change, all btrfs checksum algorithms now have
library APIs. btrfs is planned to start just using the library
directly.
This refactor also improves consistency between the BLAKE2b code
and BLAKE2s code. And as usual, it also fixes the issue where the
architecture-optimized BLAKE2b code was disabled by default.
- Add POLYVAL support to lib/crypto/, replacing the existing POLYVAL
support in crypto_shash. Reimplement HCTR2 on top of the library.
This simplifies the code and improves HCTR2 performance. As usual,
it also makes the architecture-optimized code be enabled by
default. The generic implementation of POLYVAL is greatly improved
as well.
- Clean up the BLAKE2s code
- Add FIPS self-tests for SHA-1, SHA-2, and SHA-3"
* tag 'libcrypto-updates-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ebiggers/linux: (37 commits)
fscrypt: Drop obsolete recommendation to enable optimized POLYVAL
crypto: polyval - Remove the polyval crypto_shash
crypto: hctr2 - Convert to use POLYVAL library
lib/crypto: x86/polyval: Migrate optimized code into library
lib/crypto: arm64/polyval: Migrate optimized code into library
lib/crypto: polyval: Add POLYVAL library
crypto: polyval - Rename conflicting functions
lib/crypto: x86/blake2s: Use vpternlogd for 3-input XORs
lib/crypto: x86/blake2s: Avoid writing back unchanged 'f' value
lib/crypto: x86/blake2s: Improve readability
lib/crypto: x86/blake2s: Use local labels for data
lib/crypto: x86/blake2s: Drop check for nblocks == 0
lib/crypto: x86/blake2s: Fix 32-bit arg treated as 64-bit
lib/crypto: arm, arm64: Drop filenames from file comments
lib/crypto: arm/blake2s: Fix some comments
crypto: s390/sha3 - Remove superseded SHA-3 code
crypto: sha3 - Reimplement using library API
crypto: jitterentropy - Use default sha3 implementation
lib/crypto: s390/sha3: Add optimized one-shot SHA-3 digest functions
lib/crypto: sha3: Support arch overrides of one-shot digest functions
...
Remove ansi_cprng, since it's obsolete and unused, as confirmed at
https://lore.kernel.org/r/aQxpnckYMgAAOLpZ@gondor.apana.org.au/
This was originally added in 2008, apparently as a FIPS approved random
number generator. Whether this has ever belonged upstream is
questionable. Either way, ansi_cprng is no longer usable for this
purpose, since it's been superseded by the more modern algorithms in
crypto/drbg.c, and FIPS itself no longer allows it. (NIST SP 800-131A
Rev 1 (2015) says that RNGs based on ANSI X9.31 will be disallowed after
2015. NIST SP 800-131A Rev 2 (2019) confirms they are now disallowed.)
Therefore, there is no reason to keep it around.
Suggested-by: Herbert Xu <herbert@gondor.apana.org.au>
Cc: Haotian Zhang <vulab@iscas.ac.cn>
Cc: Neil Horman <nhorman@tuxdriver.com>
Signed-off-by: Eric Biggers <ebiggers@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
driver, as well as the CEC extension to the DW-HDMI-QP driver.
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Merge tag 'v6.19-rockchip-defconfig64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/defconfig
Rockchip support for basic camera interface (CIF) and Synopsis DW-DP
driver, as well as the CEC extension to the DW-HDMI-QP driver.
* tag 'v6.19-rockchip-defconfig64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: defconfig: enable rockchip camera interface
arm64: defconfig: Enable DW HDMI QP CEC support
arm64: defconfig: Enable Rockchip extensions for Synopsys DW DP
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Enable config options for the hardare used across Fairphone 3, 4, and 5.
Then enable Novatek display panels founds on Xiaomi Pocophone F1, and
the SM8750 MTP, eUSB2 PHY found in SM8750, NSS clock controller found in
IPQ5424, the SX150x gpio expander used in QCS615 reference device, and
the support for UFS inline crypto.
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Merge tag 'qcom-arm64-defconfig-for-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/defconfig
Qualcomm Arm64 defconfig updates for v6.19
Enable config options for the hardare used across Fairphone 3, 4, and 5.
Then enable Novatek display panels founds on Xiaomi Pocophone F1, and
the SM8750 MTP, eUSB2 PHY found in SM8750, NSS clock controller found in
IPQ5424, the SX150x gpio expander used in QCS615 reference device, and
the support for UFS inline crypto.
* tag 'qcom-arm64-defconfig-for-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
arm64: defconfig: Enable SX150x GPIO expander driver
arm64: defconfig: Build NSS clock controller driver for IPQ5424
arm64: defconfig: Enable SCSI UFS Crypto and Block Inline encryption drivers
arm64: defconfig: Add M31 eUSB2 PHY config
arm64: defconfig: Enable configs for Fairphone 3, 4, 5 smartphones
arm64: defconfig: Enable two Novatek display panels for MTP8750 and Tianma
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Enable the new driver for the VRS PSEQ RTC found on Tegra234 and later.
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Merge tag 'tegra-for-6.19-arm64-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/defconfig
arm64: tegra: Default configuration changes for v6.19-rc1
Enable the new driver for the VRS PSEQ RTC found on Tegra234 and later.
* tag 'tegra-for-6.19-arm64-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: defconfig: Enable NVIDIA VRS PSEQ RTC
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
As MediaTek boards with UFS appeared some time ago, this adds a
single commit enabling the MediaTek UFS driver, allowing those
boards to boot over UFS as primary storage.
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Merge tag 'mtk-defconfig-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/defconfig
MediaTek defconfig updates
As MediaTek boards with UFS appeared some time ago, this adds a
single commit enabling the MediaTek UFS driver, allowing those
boards to boot over UFS as primary storage.
* tag 'mtk-defconfig-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux:
arm64: defconfig: Enable UFS support for MediaTek Genio 1200 EVK UFS board
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Enable the Exynos ACPM clocks driver. Samsung Exynos platforms
implement ACPM to provide support for clock configuration, PMIC
and temperature sensors.
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Tested-by: Peter Griffin <peter.griffin@linaro.org> # on gs101-oriole
Link: https://patch.msgid.link/20251010-acpm-clk-v6-5-321ee8826fd4@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20251110121344.120785-5-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Enable support for the Renesas RZ/G3S and RZ/G3E thermal drivers,
and the RZ/T2H and RZ/N2H ADC drivers in the ARM64 defconfig,
- Refresh the ARM SH-Mobile defconfig for v6.18-rc1.
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Merge tag 'renesas-arm-defconfig-for-v6.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/defconfig
Renesas ARM defconfig updates for v6.19
- Enable support for the Renesas RZ/G3S and RZ/G3E thermal drivers,
and the RZ/T2H and RZ/N2H ADC drivers in the ARM64 defconfig,
- Refresh the ARM SH-Mobile defconfig for v6.18-rc1.
* tag 'renesas-arm-defconfig-for-v6.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: defconfig: Enable RZ/T2H / RZ/N2H ADC driver
ARM: shmobile: defconfig: Refresh for v6.18-rc1
arm64: defconfig: Enable the Renesas RZ/G3E thermal driver
arm64: defconfig: Enable Renesas RZ/G3S thermal driver
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The patch "7bd291abe2d sched: Unify the SCHED_{SMT,CLUSTER,MC} Kconfig"
has enabled the SCHED_MC/SCHED_SMT by default for arm64.
So remove the redundant code in defconfig.
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Huang Shijie <shijie@os.amperecomputing.com>
Link: https://lore.kernel.org/r/20251021075704.527626-1-shijie@os.amperecomputing.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Enable support for Black Sesame Technologies (BST) platform
in the ARM64 defconfig:
- CONFIG_ARCH_BST: Enable BST SoC platform support
Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Enable the i.MX AIPSTZ driver, which is used for i.MX8MP-based boards such
as NXP's IMX8MP-EVK.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Enable i.MX95 pinctrl driver necessary for booting. Also enable the
missing drivers required for Ethernet and PCIe functionality. These
drivers are used on i.MX95 boards, including the NXP i.MX95 19x19 EVK.
The below configurations were enabled (listed with their DT nodes on
imx95.dtsi):
* CONFIG_PINCTRL_IMX_SCMI for the `scmi_iomuxc` pinctrl.
* CONFIG_CLK_IMX95_BLK_CTL for the HSIO domain clock controller
(`hsio_blk_ctl`) used by the PCIe controller.
* CONFIG_NXP_NETC_BLK_CTRL for the NETC hardware domain controller
(`netc_blk_ctrl`).
* CONFIG_NXP_ENETC4 for the Ethernet controller (`enetc_port*`).
Signed-off-by: João Paulo Gonçalves <joao.goncalves@toradex.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The Rockchip Camera Interface (CIF) is featured in many Rockchip SoCs
in different variations.
Enable the driver for it in the default configuration.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Mehdi Djait <mehdi.djait@linux.intel.com>
Signed-off-by: Michael Riesch <michael.riesch@collabora.com>
Link: https://patch.msgid.link/20240220-rk3568-vicap-v15-11-8f4915ee365d@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Enable NVIDIA VRS (Voltage Regulator Specification) RTC device module.
It provides functionality to get/set system time, retain system time
across boot, wake system from suspend and shutdown state.
Supported platforms:
- NVIDIA Jetson AGX Orin Developer Kit
- NVIDIA IGX Orin Development Kit
- NVIDIA Jetson Orin NX Developer Kit
- NVIDIA Jetson Orin Nano Developer Kit
Signed-off-by: Shubhi Garg <shgarg@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The ANX7625 bridge on the Qualcomm QCS615 Ride reference board is connected
to a Semtech SX150x GPIO expander. Enable the SX150x driver to make the
display on boards built following this design functional.
Signed-off-by: Fange Zhang <fange.zhang@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251105-enable-sx150x-gpio-expander-v3-1-2ec8dfde2c9e@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Instead of exposing the arm64-optimized SHA-3 code via arm64-specific
crypto_shash algorithms, instead just implement the sha3_absorb_blocks()
and sha3_keccakf() library functions. This is much simpler, it makes
the SHA-3 library functions be arm64-optimized, and it fixes the
longstanding issue where the arm64-optimized SHA-3 code was disabled by
default. SHA-3 still remains available through crypto_shash, but
individual architectures no longer need to handle it.
Note: to see the diff from arch/arm64/crypto/sha3-ce-glue.c to
lib/crypto/arm64/sha3.h, view this commit with 'git show -M10'.
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20251026055032.1413733-10-ebiggers@kernel.org
Signed-off-by: Eric Biggers <ebiggers@kernel.org>
The commit 4adc20ba95 ("ARM: dts: broadcom: rpi: Switch to V3D firmware
clock") causes a regression in arm64 developer setups, which stores the
kernel modules via NFS. Before this change the involved V3D clock provider
was builtin, but after this DT change the clk-raspberrypi is responsible
for V3D and for arm64/defconfig this driver is build as a kernel module.
In case these kernel modules are provided via NFS this takes too long and
the PM domain core give up before the clock driver could be loaded:
v3d fec00000.gpu: deferred probe timeout, ignoring dependency
So resolve this issue by making this critical driver builtin.
Reported-by: Mark Brown <broonie@kernel.org>
Closes: https://lore.kernel.org/linux-arm-kernel/9ebda74e-e700-4fbe-bca5-382f92417a9c@sirena.org.uk/
Fixes: 4adc20ba95 ("ARM: dts: broadcom: rpi: Switch to V3D firmware clock")
Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Link: https://lore.kernel.org/r/20251104174518.11783-1-wahrenst@gmx.net
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
NSS clock controller is needed for supplying clocks and resets to the
networking blocks for the Ethernet functions on the IPQ5424 platforms.
All boards based on the IPQ5424 SoC will require this driver to be enabled.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Link: https://lore.kernel.org/r/20251014-qcom_ipq5424_nsscc-v7-10-081f4956be02@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
These drivers will allow using the crypto functionalities of the UFS
device, like Inline Crypto Encryption. Both of these drivers are of type
'bool', so they cannot be built as modules.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://lore.kernel.org/r/20251030095509.5877-1-manivannan.sadhasivam@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The Qualcomm SM8750 SoCs use an eUSB2 PHY driver different from the
already existing M31 USB driver because it requires a connection
to an eUSB2 repeater. Thus, for USB to probe and work properly on
the Qualcomm SM8750 SoCs, enable the additional driver.
Signed-off-by: Melody Olvera <melody.olvera@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251021-knp-usb-v2-4-a2809fffcfab@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Enable drivers for Novatek NT36672A panel (used on Xiaomi Pocophone F1
Tianma, Qualcomm SDM845 SoC) and Novatek NT37801 panel (used on Qualcomm
MTP8750 development board).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20251009021507.175290-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs include three
12-Bit successive approximation A/D converters.
RZ/T2H has two ADCs with 4 channels and one with 6.
RZ/N2H has two ADCs with 4 channels and one with 15.
Enable the driver for them, as used on the RZ/T2H and RZ/N2H EVKs.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251005111323.804638-7-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Enable support for the CEC interface of the Synopsys DesignWare HDMI QP
IP block.
This is used by all boards based on RK3588 & RK3576 SoCs.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Enable Rockchip specific extensions for Synopsys DesignWare DisplayPort
driver. This is used to provide DisplayPort output support for many boards
based on RK3588 SoC.
Signed-off-by: Andy Yan <andyshrk@163.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Enable the UFS related settings to support Genio 1200 EVK UFS board.
This board uses UFS as the boot device and also the main storage.
This includes support for:
- CONFIG_SCSI_UFS_MEDIATEK
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Enable the Renesas RZ/G3E thermal driver, as used on the Renesas
RZ/G3E SMARC EVK board.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250917170202.197929-5-john.madieu.xa@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Only a small set up updates, enabling a few drivers for Artpec, THead,
Renesas and Broadcom chips, and cleaning out some Qualcomm options that
were removed previously.
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Merge tag 'soc-defconfig-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC defconfig updates from Arnd Bergmann:
"Only a small set up updates, enabling a few drivers for Artpec, THead,
Renesas and Broadcom chips, and cleaning out some Qualcomm options
that were removed previously"
* tag 'soc-defconfig-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
ARM: configs: u8500: Set NFC_SHDLC as built-in
riscv: defconfig: Enable MMP_PDMA support for SpacemiT K1 SoC
riscv: defconfig: run savedefconfig to reorder it
ARM: defconfig: Remove obsolete CONFIG_USB_EHCI_MSM
arm64: defconfig: Enable Marvell WiFi-Ex USB driver
arm64: defconfig: Enable BCM2712 on-chip pin controller driver
arm64: defconfig: Enable Axis ARTPEC SoC
ARM: s3c6400_defconfig: Drop MTD_NAND_S3C2410
ARM: defconfig: pxa: Remove duplicate CONFIG_USB_GPIO_VBUS entry
ARM: defconfig: cleanup orphaned CONFIGs
arm64: defconfig: enable i.MX91 pinctrl
arm64: defconfig: Enable X1P42100 GPUCC driver
arm64: defconfig: Enable QCS615 clock controllers
arm64: defconfig: Enable the RZ/V2H(P) RSPI driver
arm64: defconfig: Enable Renesas RZ/T2H serial SCI
Enable STMicroelectronics STM32 DMA3 support as module.
STM32 DMA3 is used among others by STM32 Octo SPI driver on
STM32MP257F-EV1 board.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250821-upstream_defconfig_enable_stm32_dma3-v1-1-d9c1b71883d9@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
please pull the following:
- Andrea enables the RP1 pinctrl driver which is necessary for the
Raspberry Pi 5 systems
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Merge tag 'arm-soc/for-6.18/defconfig-arm64' of https://github.com/Broadcom/stblinux into soc/defconfig
This pull request contains ARM64 defconfig changes for Broadcom SoCs,
please pull the following:
- Andrea enables the RP1 pinctrl driver which is necessary for the
Raspberry Pi 5 systems
* tag 'arm-soc/for-6.18/defconfig-arm64' of https://github.com/Broadcom/stblinux:
arm64: defconfig: Enable BCM2712 on-chip pin controller driver
Link: https://lore.kernel.org/r/20250910171910.666401-1-florian.fainelli@broadcom.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
MBa91xxCA (imx93-tqma9352-mba91xxca.dts) features a soldered,
non-pluggable USB attached WiFi module. lsusb says:
ID 1286:204e Marvell Semiconductor, Inc. Bluetooth and Wireless LAN Composite Device
Enable the corresponding driver.
To: Shawn Guo <shawnguo@kernel.org>
To: Fabio Estevam <festevam@gmail.com>
To: Sascha Hauer <s.hauer@pengutronix.de>
Cc: imx@lists.linux.dev
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Select the on-chip pin controller driver for BCM2712 SoC.
On RapsberryPi 5 devices it is primarily needed to operate the
bluetooth and WiFi devices, to configure the uSD interface
and the power button.
Signed-off-by: Andrea della Porta <andrea.porta@suse.com>
Link: https://lore.kernel.org/all/38704a5ab6913845bbf9178170e83004ab3e8fcf.1756372805.git.andrea.porta@suse.com/
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
Enable the Axis ARTPEC-8 SoC in arm64 defconfig.
Signed-off-by: SungMin Park <smn1196@coasia.com>
Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
Link: https://lore.kernel.org/r/20250901051926.59970-7-ravi.patel@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Enable i.MX91 pinctrl driver for booting the system.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Pengfei Li <pengfei.li_1@nxp.com>
Signed-off-by: Joy Zou <joy.zou@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
In order to enable GPU support in X1P42100-CRD and other similar
laptops with Snapdragon X1P42100 SoC, enable X1P42100 GPUCC driver
as a module.
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250623-x1p-adreno-v4-2-d2575c839cbb@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Enable the QCS615 display, video, camera and graphics clock controller
for their respective functionalities on the Qualcomm QCS615 ride
platform.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-10-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Selects RZ/T2H (aka r9a09g077) SCI (serial) specific code, as used on
the RZ/T2H and RZ/N2H EVKs.
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
Link: https://lore.kernel.org/20250515141828.43444-11-thierry.bultel.yh@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
As usual, more drivers get enabled in the defconfigs, to support newly
added hardware drivers.
There is one change for Tegra that modifies the Kconfig file at the same
time, and the NXP arm32 defconfigs get a refresh.
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Merge tag 'soc-defconfig-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC defconfig updates from Arnd Bergmann:
"As usual, more drivers get enabled in the defconfigs, to support newly
added hardware drivers.
There is one change for Tegra that modifies the Kconfig file at the
same time, and the NXP arm32 defconfigs get a refresh"
* tag 'soc-defconfig-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (25 commits)
arm: multi_v7_defconfig: Enable TPS65219 regulator
arm: omap2plus_defconfig: Enable TPS65219 regulator
arm64: defconfig: Enable Tegra241 and Tegra264
riscv: defconfig: spacemit: enable sdhci driver for K1 SoC
riscv: defconfig: Enable PWM support for SpacemiT K1 SoC
riscv: defconfig: Remove CONFIG_SND_SOC_STARFIVE=m
arm64: defconfig: Enable Tegra HSP and BPMP
ARM: imx_v6_v7_defconfig: select CONFIG_USB_HSIC_USB3503
ARM: imx_v6_v7_defconfig: select CONFIG_INPUT_PWM_BEEPER
ARM: imx_v6_v7_defconfig: cleanup with savedefconfig
ARM: mxs_defconfig: select new drivers used by imx28-amarula-rmm
ARM: mxs_defconfig: Cleanup mxs_defconfig
arm64: defconfig: enable further Rockchip platform drivers
arm64: defconfig: enable Samsung PMIC over ACPM
arm64: defconfig: enable Maxim max77759 driver
ARM: configs: sama5_defconfig: Select CONFIG_WILC1000_SDIO
ARM: shmobile: defconfig: Refresh for v6.16-rc2
arm64: defconfig: Enable RZ/V2H(P) USB2 PHY controller reset driver
arm64: defconfig: add S32G RTC module support
arm64: defconfig: Drop unneeded unselectable sound drivers
...
These five newly supported chips come with both devicetree descriptions
and the changes to wire them up to the build system for easier bisection.
The chips in question are:
- Marvell PXA1908 was the first 64-bit mobile phone chip from Marvell
in the product line that started with the Digital StrongARM SA1100
based PDAs and continued with the Intel PXA2xx that dominated early
smartphones. This one only made it only into a few products before the
entire product line was cut in 2015.
- The QiLai SoC is made by RISC-V core designer Andes Technologies
and is in the 'Voyager' reference board in MicroATX form factor.
It uses four in-order AX45MP cores, which is the midrange product
from Andes.
- CIX P1 is one of the few Arm chips designed for small workstations,
and this one uses 12 Cortex-A720/A520 cores, making it also one
of the only ARMv9.2 machines that one can but at the moment.
- Axiado AX3000 is an embedded chip with relative small Cortex-A53
CPU cores described as a "Trusted Control/Compute Unit" that can
be used as a BMC in servers. In addition to the usual I/O, this one
comes with 10GBit ethernet and and a 4TOPS NPU.
- Sophgo SG2000 is an embedded chip that comes with both RISC-V
and Arm cores that can run Linux. This was already supported for
RISC-V but now it also works on Arm
One more chip, the Black Sesame C1200 did not make it in tirm for the
merge window.
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Merge tag 'soc-newsoc-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull new SoC support from Arnd Bergmann:
"These five newly supported chips come with both devicetree
descriptions and the changes to wire them up to the build system for
easier bisection.
The chips in question are:
- Marvell PXA1908 was the first 64-bit mobile phone chip from Marvell
in the product line that started with the Digital StrongARM SA1100
based PDAs and continued with the Intel PXA2xx that dominated early
smartphones. This one only made it only into a few products before
the entire product line was cut in 2015.
- The QiLai SoC is made by RISC-V core designer Andes Technologies
and is in the 'Voyager' reference board in MicroATX form factor. It
uses four in-order AX45MP cores, which is the midrange product from
Andes.
- CIX P1 is one of the few Arm chips designed for small workstations,
and this one uses 12 Cortex-A720/A520 cores, making it also one of
the only ARMv9.2 machines that one can but at the moment.
- Axiado AX3000 is an embedded chip with relative small Cortex-A53
CPU cores described as a "Trusted Control/Compute Unit" that can be
used as a BMC in servers. In addition to the usual I/O, this one
comes with 10GBit ethernet and and a 4TOPS NPU.
- Sophgo SG2000 is an embedded chip that comes with both RISC-V and
Arm cores that can run Linux. This was already supported for RISC-V
but now it also works on Arm
One more chip, the Black Sesame C1200 did not make it in tirm for the
merge window"
* tag 'soc-newsoc-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits)
arm64: defconfig: Enable rudimentary Sophgo SG2000 support
arm64: Add SOPHGO SOC family Kconfig support
arm64: dts: sophgo: Add Duo Module 01 Evaluation Board
arm64: dts: sophgo: Add Duo Module 01
arm64: dts: sophgo: Add initial SG2000 SoC device tree
MAINTAINERS: Add entry for Axiado
arm64: defconfig: enable the Axiado family
arm64: dts: axiado: Add initial support for AX3000 SoC and eval board
arm64: add Axiado SoC family
dt-bindings: i3c: cdns: add Axiado AX3000 I3C controller
dt-bindings: serial: cdns: add Axiado AX3000 UART controller
dt-bindings: gpio: cdns: add Axiado AX3000 GPIO variant
dt-bindings: gpio: cdns: convert to YAML
dt-bindings: arm: axiado: add AX3000 EVK compatible strings
dt-bindings: vendor-prefixes: Add Axiado Corporation
MAINTAINERS: Add CIX SoC maintainer entry
arm64: dts: cix: Add sky1 base dts initial support
dt-bindings: clock: cix: Add CIX sky1 scmi clock id
arm64: defconfig: Enable CIX SoC
mailbox: add CIX mailbox driver
...
There are a few new variants of existing chips:
- mt6572 is an older mobile phone chip from mediatek that was
extremely popular a decade ago but never got upstreamed until now.
- exynos2200 is a recent high-end mobile phone chip used in a
few Samsung phones like the Galaxy S22
- Renesas R-Car V4M-7 (R8A779H2) is an updated version of R-Car V4M
(R8A779H0) and used in automotive applications
- Tegra264 is a new chip from NVIDIA, but support is fairly minimal
for now, and not much information is public about it.
There are five more chips in a separate branch, as those are new
chip families that I merged along with the necessary infrastructure.
New board support is not that exciting, with a total of 33 newly
added machines here:
- Evaluation platforms for the chips above, plus TI am62d2 and
Sophgo sg2042.
- Six 32-bit industrial boards based on stm32, imx6 and am33 chips,
plus eight 64-bit rockchips rk33xx/rk35xx, am62d2, t527, imx8 and
imx95.
- Two newly added ASPEED BMC based motherboards, and one that got
removed
- Phones and Tablets based on 32-bit mt6572, tegra30 and 64-bit
msm8976 SoCs
- Three Laptops based on Mediatek mt8186 and Qualcomm Snapdragon X1
- A set-top box based on Amlogic meson-gxm.
Updates for existing machines are spread over all the above families.
One notable change here is support for the RP1 I/O chip used in
Raspberry Pi 5.
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Merge tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC devicetree updates from Arnd Bergmann:
"There are a few new variants of existing chips:
- mt6572 is an older mobile phone chip from mediatek that was
extremely popular a decade ago but never got upstreamed until now
- exynos2200 is a recent high-end mobile phone chip used in a few
Samsung phones like the Galaxy S22
- Renesas R-Car V4M-7 (R8A779H2) is an updated version of R-Car V4M
(R8A779H0) and used in automotive applications
- Tegra264 is a new chip from NVIDIA, but support is fairly minimal
for now, and not much information is public about it
There are five more chips in a separate branch, as those are new chip
families that I merged along with the necessary infrastructure.
New board support is not that exciting, with a total of 33 newly added
machines here:
- Evaluation platforms for the chips above, plus TI am62d2 and Sophgo
sg2042
- Six 32-bit industrial boards based on stm32, imx6 and am33 chips,
plus eight 64-bit rockchips rk33xx/rk35xx, am62d2, t527, imx8 and
imx95
- Two newly added ASPEED BMC based motherboards, and one that got
removed
- Phones and Tablets based on 32-bit mt6572, tegra30 and 64-bit
msm8976 SoCs
- Three Laptops based on Mediatek mt8186 and Qualcomm Snapdragon X1
- A set-top box based on Amlogic meson-gxm
Updates for existing machines are spread over all the above families.
One notable change here is support for the RP1 I/O chip used in
Raspberry Pi 5"
* tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (606 commits)
riscv: dts: sophgo: fix mdio node name for CV180X
riscv: dts: sophgo: sophgo-srd3-10: reserve uart0 device
riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree
riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree
dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings
riscv: dts: sophgo: add ethernet GMAC device for sg2042
riscv: dts: sophgo: Enable ethernet device for Huashan Pi
riscv: dts: sophgo: Add mdio multiplexer device for cv18xx
riscv: dts: sophgo: Add ethernet device for cv18xx
riscv: dts: sophgo: sg2044: add pmu configuration
riscv: dts: sophgo: sg2044: add ziccrse extension
riscv: dts: sophgo: add zfh for sg2042
riscv: dts: sophgo: add ziccrse for sg2042
riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree
riscv: dts: sophgo: sg2044: add PCIe device support for SG2044
riscv: dts: sophgo: sg2044: add MSI device support for SG2044
riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC
riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC
dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000
riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size property
...
This is the main crypto library pull request for 6.17. The main focus
this cycle is on reorganizing the SHA-1 and SHA-2 code, providing
high-quality library APIs for SHA-1 and SHA-2 including HMAC support,
and establishing conventions for lib/crypto/ going forward:
- Migrate the SHA-1 and SHA-512 code (and also SHA-384 which shares
most of the SHA-512 code) into lib/crypto/. This includes both the
generic and architecture-optimized code. Greatly simplify how the
architecture-optimized code is integrated. Add an easy-to-use
library API for each SHA variant, including HMAC support. Finally,
reimplement the crypto_shash support on top of the library API.
- Apply the same reorganization to the SHA-256 code (and also SHA-224
which shares most of the SHA-256 code). This is a somewhat smaller
change, due to my earlier work on SHA-256. But this brings in all
the same additional improvements that I made for SHA-1 and SHA-512.
There are also some smaller changes:
- Move the architecture-optimized ChaCha, Poly1305, and BLAKE2s code
from arch/$(SRCARCH)/lib/crypto/ to lib/crypto/$(SRCARCH)/. For
these algorithms it's just a move, not a full reorganization yet.
- Fix the MIPS chacha-core.S to build with the clang assembler.
- Fix the Poly1305 functions to work in all contexts.
- Fix a performance regression in the x86_64 Poly1305 code.
- Clean up the x86_64 SHA-NI optimized SHA-1 assembly code.
Note that since the new organization of the SHA code is much simpler,
the diffstat of this pull request is negative, despite the addition of
new fully-documented library APIs for multiple SHA and HMAC-SHA
variants. These APIs will allow further simplifications across the
kernel as users start using them instead of the old-school crypto API.
(I've already written a lot of such conversion patches, removing over
1000 more lines of code. But most of those will target 6.18 or later.)
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Merge tag 'libcrypto-updates-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ebiggers/linux
Pull crypto library updates from Eric Biggers:
"This is the main crypto library pull request for 6.17. The main focus
this cycle is on reorganizing the SHA-1 and SHA-2 code, providing
high-quality library APIs for SHA-1 and SHA-2 including HMAC support,
and establishing conventions for lib/crypto/ going forward:
- Migrate the SHA-1 and SHA-512 code (and also SHA-384 which shares
most of the SHA-512 code) into lib/crypto/. This includes both the
generic and architecture-optimized code. Greatly simplify how the
architecture-optimized code is integrated. Add an easy-to-use
library API for each SHA variant, including HMAC support. Finally,
reimplement the crypto_shash support on top of the library API.
- Apply the same reorganization to the SHA-256 code (and also SHA-224
which shares most of the SHA-256 code). This is a somewhat smaller
change, due to my earlier work on SHA-256. But this brings in all
the same additional improvements that I made for SHA-1 and SHA-512.
There are also some smaller changes:
- Move the architecture-optimized ChaCha, Poly1305, and BLAKE2s code
from arch/$(SRCARCH)/lib/crypto/ to lib/crypto/$(SRCARCH)/. For
these algorithms it's just a move, not a full reorganization yet.
- Fix the MIPS chacha-core.S to build with the clang assembler.
- Fix the Poly1305 functions to work in all contexts.
- Fix a performance regression in the x86_64 Poly1305 code.
- Clean up the x86_64 SHA-NI optimized SHA-1 assembly code.
Note that since the new organization of the SHA code is much simpler,
the diffstat of this pull request is negative, despite the addition of
new fully-documented library APIs for multiple SHA and HMAC-SHA
variants.
These APIs will allow further simplifications across the kernel as
users start using them instead of the old-school crypto API. (I've
already written a lot of such conversion patches, removing over 1000
more lines of code. But most of those will target 6.18 or later)"
* tag 'libcrypto-updates-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ebiggers/linux: (67 commits)
lib/crypto: arm64/sha512-ce: Drop compatibility macros for older binutils
lib/crypto: x86/sha1-ni: Convert to use rounds macros
lib/crypto: x86/sha1-ni: Minor optimizations and cleanup
crypto: sha1 - Remove sha1_base.h
lib/crypto: x86/sha1: Migrate optimized code into library
lib/crypto: sparc/sha1: Migrate optimized code into library
lib/crypto: s390/sha1: Migrate optimized code into library
lib/crypto: powerpc/sha1: Migrate optimized code into library
lib/crypto: mips/sha1: Migrate optimized code into library
lib/crypto: arm64/sha1: Migrate optimized code into library
lib/crypto: arm/sha1: Migrate optimized code into library
crypto: sha1 - Use same state format as legacy drivers
crypto: sha1 - Wrap library and add HMAC support
lib/crypto: sha1: Add HMAC support
lib/crypto: sha1: Add SHA-1 library functions
lib/crypto: sha1: Rename sha1_init() to sha1_init_raw()
crypto: x86/sha1 - Rename conflicting symbol
lib/crypto: sha2: Add hmac_sha*_init_usingrawkey()
lib/crypto: arm/poly1305: Remove unneeded empty weak function
lib/crypto: x86/poly1305: Fix performance regression on short messages
...
Sophgo:
Add support for Duo Module 01 Evaluation Board.
This board uses SG2000(old codename CV181xH),
which is dual-arch, RISC-V and ARM64. This
patch add the support for ARM64.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
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Merge tag 'arm-sophgo-dt-for-v6.17' of https://github.com/sophgo/linux into soc/newsoc
ARM Devicetrees for v6.17
Sophgo:
Add support for Duo Module 01 Evaluation Board.
This board uses SG2000(old codename CV181xH),
which is dual-arch, RISC-V and ARM64. This
patch add the support for ARM64.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
* tag 'arm-sophgo-dt-for-v6.17' of https://github.com/sophgo/linux:
arm64: defconfig: Enable rudimentary Sophgo SG2000 support
arm64: Add SOPHGO SOC family Kconfig support
arm64: dts: sophgo: Add Duo Module 01 Evaluation Board
arm64: dts: sophgo: Add Duo Module 01
arm64: dts: sophgo: Add initial SG2000 SoC device tree
Link: https://lore.kernel.org/r/MAUPR01MB11072C4B088AAC02268044E95FE5FA@MAUPR01MB11072.INDPRD01.PROD.OUTLOOK.COM
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Enable ARCH_SOPHGO, pinctrl (built-in, required to boot), ADC as module.
This defconfig is able to boot from SD card on Milk-V Duo Module 01
evalboard.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Link: https://lore.kernel.org/r/20250612132844.767216-7-alexander.sverdlin@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
Support for the AX3000 SoC, from Harshit Shah <hshah@axiado.com>:
The AX3000 is a multi-core system-on-chip featuring four ARM Cortex-A53
cores, secure vault, hardware firewall, and AI acceleration engines. This
initial support enables basic bring-up of the SoC and evaluation platform
with CPU, timer, UART, and I3C functionality.
The series begins by adding the "axiado" vendor prefix and compatible
strings for the SoC and board. It then introduces the device tree files
and minimal ARCH_AXIADO platform support in arm64.
* newsoc/axiado:
MAINTAINERS: Add entry for Axiado
arm64: defconfig: enable the Axiado family
arm64: dts: axiado: Add initial support for AX3000 SoC and eval board
arm64: add Axiado SoC family
dt-bindings: i3c: cdns: add Axiado AX3000 I3C controller
dt-bindings: serial: cdns: add Axiado AX3000 UART controller
dt-bindings: gpio: cdns: add Axiado AX3000 GPIO variant
dt-bindings: gpio: cdns: convert to YAML
dt-bindings: arm: axiado: add AX3000 EVK compatible strings
dt-bindings: vendor-prefixes: Add Axiado Corporation
Enable the Axiado SoC family in the arm64 defconfig.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Harshit Shah <hshah@axiado.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Enable the HSP and BPMP via the configuration instead of selecting them,
which can lead to problems. Also enable support for Tegra241, which was
never done after support for it was added, and Tegra264.
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Merge tag 'tegra-for-6.17-arm64-defconfig' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/defconfig
arm64: tegra: Default configuration updates for v6.17-rc1
Enable the HSP and BPMP via the configuration instead of selecting them,
which can lead to problems. Also enable support for Tegra241, which was
never done after support for it was added, and Tegra264.
* tag 'tegra-for-6.17-arm64-defconfig' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: defconfig: Enable Tegra241 and Tegra264
arm64: defconfig: Enable Tegra HSP and BPMP
Link: https://lore.kernel.org/r/20250711220943.2389322-8-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
1. Multiple SoCs (including Samsung, Apple): switch sound to module from
a built-in, because it is not necessary for booting. Also drop
redundant sound codec options.
2. Enable PMIC drivers for Google GS101 Pixel 6 phones: MAX77759 and
Samsung PMIC over ACPM protocol.
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Merge tag 'samsung-defconfig-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/defconfig
Samsung SoC defconfig changes for v6.17
1. Multiple SoCs (including Samsung, Apple): switch sound to module from
a built-in, because it is not necessary for booting. Also drop
redundant sound codec options.
2. Enable PMIC drivers for Google GS101 Pixel 6 phones: MAX77759 and
Samsung PMIC over ACPM protocol.
* tag 'samsung-defconfig-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: defconfig: enable Samsung PMIC over ACPM
arm64: defconfig: enable Maxim max77759 driver
arm64: defconfig: Drop unneeded unselectable sound drivers
arm64: defconfig: Switch SOUND to module
Link: https://lore.kernel.org/r/20250709191523.171359-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Patches from Peter Chen <peter.chen@cixtech.com>:
Cixtech P1 (internal name sky1) is high performance generic Armv9 SoC.
Orion O6 is the Arm V9 Motherboard built by Radxa. You could find brief
introduction for SoC and related boards at:
https://radxa.com/products/orion/o6#overview
Currently, to run upstream kernel at Orion O6 board, you need to
use BIOS released by Radxa, and add "clk_ignore_unused=1" at bootargs.
https://docs.radxa.com/en/orion/o6/bios/install-bios
In this series, we add initial SoC and board support for Kernel building.
Since mailbox is used for SCMI clock communication, mailbox driver is added
in this series for the minimum SoC support.
Patch 1-2: add dt-binding doc for CIX and its sky1 SoC
Patch 3: add Arm64 build support
Patch 4-5: add CIX mailbox driver which needs to support SCMI clock protocol.
Patch 6: add Arm64 defconfig support
Patch 7-8: add initial dts support for SoC and Orion O6 board
Patch 9: add MAINTAINERS entry
* newsoc/cix-p1:
MAINTAINERS: Add CIX SoC maintainer entry
arm64: dts: cix: Add sky1 base dts initial support
dt-bindings: clock: cix: Add CIX sky1 scmi clock id
arm64: defconfig: Enable CIX SoC
mailbox: add CIX mailbox driver
dt-bindings: mailbox: add cix,sky1-mbox
arm64: Kconfig: add ARCH_CIX for cix silicons
dt-bindings: arm: add CIX P1 (SKY1) SoC
dt-bindings: vendor-prefixes: Add CIX Technology Group Co., Ltd.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Enable CIX SoC support at ARM64 defconfig
- Enable CIX mailbox
At CIX SoC platforms, the clock handling uses Arm SCMI protocol,
the physical clock access is at sub processor, so it needs to enable
mailbox by default.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Peter Chen <peter.chen@cixtech.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Instead of exposing the arm64-optimized SHA-1 code via arm64-specific
crypto_shash algorithms, instead just implement the sha1_blocks()
library function. This is much simpler, it makes the SHA-1 library
functions be arm64-optimized, and it fixes the longstanding issue where
the arm64-optimized SHA-1 code was disabled by default. SHA-1 still
remains available through crypto_shash, but individual architectures no
longer need to handle it.
Remove support for SHA-1 finalization from assembly code, since the
library does not yet support architecture-specific overrides of the
finalization. (Support for that has been omitted for now, for
simplicity and because usually it isn't performance-critical.)
To match sha1_blocks(), change the type of the nblocks parameter and the
return value of __sha1_ce_transform() from int to size_t. Update the
assembly code accordingly.
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20250712232329.818226-9-ebiggers@kernel.org
Signed-off-by: Eric Biggers <ebiggers@kernel.org>
The v6.16 driver and DeviceTree updates described and implemented CPU
frequency scaling for the Qualcomm X Elite platform. But the necessary
CPUCP mailbox driver was not enabled, resulting in a series of error
messages being logged during boot (and no CPU frequency scaling).
Enable the missing drivers to silence the errors, and enable CPU
frequency scaling on this platform.
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Merge tag 'qcom-arm64-defconfig-fixes-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes
Qualcomm Arm64 defconfig fixes for v6.16
The v6.16 driver and DeviceTree updates described and implemented CPU
frequency scaling for the Qualcomm X Elite platform. But the necessary
CPUCP mailbox driver was not enabled, resulting in a series of error
messages being logged during boot (and no CPU frequency scaling).
Enable the missing drivers to silence the errors, and enable CPU
frequency scaling on this platform.
* tag 'qcom-arm64-defconfig-fixes-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
arm64: defconfig: Enable Qualcomm CPUCP mailbox driver
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Enable the STM32 timer drivers: MFD, counter, PWM and trigger as module.
These drivers can be used on STM32MP25.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Link: https://lore.kernel.org/r/20250110091922.980627-6-fabrice.gasnier@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
the following:
- Andrea updates the defconfig to enable the RP1 misc, clock and gpio
drivers as as well as turn on CONFIG_OF_OVERLAY which is necessary to
apply the RP1 overlay file
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Merge tag 'arm-soc/for-6.17/defconfig-arm64' of https://github.com/Broadcom/stblinux into soc/defconfig
This pull request contains ARM64 defconfig updates for 6.17, please pull
the following:
- Andrea updates the defconfig to enable the RP1 misc, clock and gpio
drivers as as well as turn on CONFIG_OF_OVERLAY which is necessary to
apply the RP1 overlay file
* tag 'arm-soc/for-6.17/defconfig-arm64' of https://github.com/Broadcom/stblinux:
arm64: defconfig: Enable OF_OVERLAY option
arm64: defconfig: Enable RP1 misc/clock/gpio drivers
Link: https://lore.kernel.org/r/20250630190216.1518354-1-florian.fainelli@broadcom.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Instead of exposing the arm64-optimized SHA-512 code via arm64-specific
crypto_shash algorithms, instead just implement the sha512_blocks()
library function. This is much simpler, it makes the SHA-512 (and
SHA-384) library functions be arm64-optimized, and it fixes the
longstanding issue where the arm64-optimized SHA-512 code was disabled
by default. SHA-512 still remains available through crypto_shash, but
individual architectures no longer need to handle it.
To match sha512_blocks(), change the type of the nblocks parameter of
the assembly functions from int or 'unsigned int' to size_t. Update the
ARMv8 CE assembly function accordingly. The scalar assembly function
actually already treated it as size_t.
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20250630160320.2888-9-ebiggers@kernel.org
Signed-off-by: Eric Biggers <ebiggers@kernel.org>
Enable the rockchip-dfi driver as a module, which is used on RK3588 as
well as RK3568 and RK3399 to measure memory bandwidth. For this, we also
enable PM_DEVFREQ_EVENT, which is a requirement for this driver.
Also enable the rockchip-rga driver as a module, which is used on
various Rockchip SoCs, including RK3588 and RK3399, to provide 2d
accelerated image transformations through a V4L2 interface.
Suggested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20250626-rk3588-defconfig-v2-1-ae6720964b01@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Enable the Samsung s2mpg1x driver as this is used by the gs101-oriole
and gs101-raven (Google Pixel 6 and Pixel 6 Pro) boards.
It communicates over ACPM instead of I2C, hence the additional
defconfig item.
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20250627-gs101-reboot3-v1-1-c3ae49657b1f@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
