2 Commits

Author	SHA1	Message	Date
Ryan Chen	9e84fd546d	arm64: dts: aspeed: Fix duplicate pinctrl labels and address scheme ... A report from shashiko-bot highlighted some concerns concurrent to application of the series[1]. Fix duplicate pinctrl_tach{0-15} and pinctrl_n{cts,dcd,dsr,ri}5 labels in aspeed-g7-soc1-pinctrl.dtsi. These didn't cause errors from dtc because dtc accepts duplicate labels for duplicate nodes specified through a node reference[2]. Drop the cpu-index from secondary/tertiary container nodes: reduce the "#address-cells" from 2 to 1 and update unit-addresses and reg accordingly. The 2-cell scheme was proposed in an early mailing list sketch to prompt discussion[3], but the design evolved in ways that made it unnecessary. Also remove URL comments from the DTS. The links were to comments in the kernel sources with discussion justifying the approach, but are not necessary to carry forward. [arj: Extend discussion in the commit message] Link: https://lore.kernel.org/all/20260609025708.ADBFE1F00893@smtp.kernel.org/ [1] Link: https://lore.kernel.org/all/b226339bb2abe42ce23e90eadbc654b426131083.camel@codeconstruct.com.au/ [2] Link: https://lore.kernel.org/all/1a2ca78746e00c2ec4bfc2953a897c48376ed36f.camel@codeconstruct.com.au/ [3] Suggested-by: Andrew Jeffery <andrew@codeconstruct.com.au> Fixes: e77bb5dc57 ("arm64: dts: aspeed: Add initial AST27xx SoC device tree") Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Link: https://patch.msgid.link/20260611-dtsi_fix-v1-1-ef2b7cd86d6d@aspeedtech.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Link: https://lore.kernel.org/r/20260612-aspeed-arm64-dt-v1-1-d1d1a4737905@codeconstruct.com.au Signed-off-by: Arnd Bergmann <arnd@arndb.de>	2026-06-12 12:39:49 +02:00
Ryan Chen	e77bb5dc57	arm64: dts: aspeed: Add initial AST27xx SoC device tree ... Add initial device tree support for the ASPEED AST27xx family, the 8th-generation Baseboard Management Controller (BMC) SoCs. AST27xx SOC Family - https://www.aspeedtech.com/server_ast2700/ - https://www.aspeedtech.com/server_ast2720/ - https://www.aspeedtech.com/server_ast2750/ The AST27xx features a dual-SoC architecture consisting of two dies, referred to as SoC0 and SoC1 - interconnected through an internal proprietary bus. Both SoCs share the same address decoding scheme, while each maintains independent clock and reset domains. - SoC0 (CPU die): contains a quad-core Cortex-A35 cluster and two Cortex-M4 cores, along with high-speed peripherals. - SoC1 (I/O die): includes the BootMCU (responsible for system boot) and its own clock/reset domains low-speed peripherals. The device tree describes the SoC0 and SoC1 domains and their peripheral layouts. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Link: https://lore.kernel.org/r/20260609-upstream_ast2700-v9-3-f631752f0cb1@aspeedtech.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>	2026-06-09 18:24:42 +02:00