The "Other Logic Block" found in the EyeQ6Lplus from Mobileye provides
various functions for the controllers present in the SoC.
The OLB produces 22 clocks derived from its input, which is connected
to the main oscillator of the SoC.
It provides reset signals via two reset domains.
It also controls 32 pins to be either a GPIO or an alternate function.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
OLB on EyeQ5 ("mobileye,eyeq5-olb" compatible) is now declared as a
generic PHY provider. Under the hood, it provides Ethernet RGMII/SGMII
PHY support for both MAC instances.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Some compatibles expose a single clock. For those, we used to let them
using `#clock-cells = <0>` (ie <&olb> reference rather than <&olb 0>).
Switch away from that: enforce a cell for all compatibles. This is more
straight forward, and avoids devicetree changes whenever a compatible
goes from exposing a single clock to multiple ones. Also, dt-bindings
get simpler.
*This is an ABI break*. Change it while EyeQ5 platform support is at its
infancy, without any user. More clocks might hide in each OLB as some
registers are still unknown.
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Link: https://lore.kernel.org/r/20241106-mbly-clk-v2-1-84cfefb3f485@bootlin.com
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add documentation to describe the "Other Logic Block" system-controller.
It deals with three platforms: EyeQ5, EyeQ6L and EyeQ6H. First two have
a single instance, whereas EyeQ6H has seven named instances.
Features provided are:
- Clocks, children to main crystal. Some PLLs and divider clocks.
- Resets. Some instances DO NOT have reset.
- Pinctrl. Only EyeQ5 has such feature.
Those are NOT the only features exposed in OLB system-controllers! Many
individual registers, related to IP block integration, can be found.
Additional features will be exposed over time.
We simplify devicetree phandles to OLB in two ways:
- Compatibles exposing a single clock do not ask for a index argument.
This means we use EyeQ6H OLB south (it has four clocks):
clocks = <&olb_south EQ6HC_SOUTH_PLL_PER>;
But use EyeQ6H OLB east (it has one clock):
clocks = <&olb_east>;
- Compatibles exposing a single reset domain do not ask for a domain
index, only a reset index.
This means we use EyeQ5 OLB (it has three domains):
resets = <&olb 0 10>;
But use EyeQ6H west reset (it has one domain):
resets = <&olb_west 3>;
About pinctrl subnodes: all pins have two functionality, either GPIO or
something-else. The latter is pin dependent, we express constraints
using many if-then.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
