The Cix Sky1 Audio Subsystem (AUDSS) Clock and Reset Unit (CRU)
groups clock muxing, gating and block-level software reset control
in a single register block.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Joakim Zhang <joakim.zhang@cixtech.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
There are two system control on Cix sky1 Soc. One is located in S0 domain,
and the other is located in S5 domain. The system control contains resets,
usb typeC and more. At this point, only the reset controller is embedded
as usb typeC uses it by phandle.
Signed-off-by: Gary Yang <gary.yang@cixtech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
