github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-06-03 12:03:54 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

drm/amd/display: Revert Add left edge pixel + ODM pipe split

Browse Source 
This reverts commit e2fdd5c525 ("drm/amd/display: Add left edge pixel for
YCbCr422/420 + ODM pipe split")

Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: George Shen <george.shen@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Gabe Teeger <gabe.teeger@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Gabe Teeger 2024-02-28 12:42:57 -05:00 committed by Alex Deucher
parent e2fdd5c525
commit ffd8e4a326
5 changed files with 0 additions and 57 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/amd/display/dc/core/dc.c
View File

@ -3167,10 +3167,6 @@ static bool update_planes_and_stream_state(struct dc *dc,
if (otg_master && otg_master->stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE)
resource_build_test_pattern_params(&context->res_ctx, otg_master);
if (otg_master && (otg_master->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422 ||
otg_master->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420))
resource_build_subsampling_params(&context->res_ctx, otg_master);
}
}

37
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
View File

@ -828,16 +828,6 @@ static struct rect calculate_odm_slice_in_timing_active(struct pipe_ctx *pipe_ct
stream->timing.v_border_bottom +
stream->timing.v_border_top;
/* Recout for ODM slices after the first slice need one extra left edge pixel
* for 3-tap chroma subsampling.
*/
if (odm_slice_idx > 0 &&
(pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422 ||
pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)) {
odm_rec.x -= 1;
odm_rec.width += 1;
}
return odm_rec;
}
@ -1454,7 +1444,6 @@ void resource_build_test_pattern_params(struct resource_context *res_ctx,
enum controller_dp_test_pattern controller_test_pattern;
enum controller_dp_color_space controller_color_space;
enum dc_color_depth color_depth = otg_master->stream->timing.display_color_depth;
enum dc_pixel_encoding pixel_encoding = otg_master->stream->timing.pixel_encoding;
int h_active = otg_master->stream->timing.h_addressable +
otg_master->stream->timing.h_border_left +
otg_master->stream->timing.h_border_right;
@ -1486,36 +1475,10 @@ void resource_build_test_pattern_params(struct resource_context *res_ctx,
else
params->width = last_odm_slice_width;
/* Extra left edge pixel is required for 3-tap chroma subsampling. */
if (i != 0 && (pixel_encoding == PIXEL_ENCODING_YCBCR422 ||
pixel_encoding == PIXEL_ENCODING_YCBCR420)) {
params->offset -= 1;
params->width += 1;
}
offset += odm_slice_width;
}
}
void resource_build_subsampling_params(struct resource_context *res_ctx,
struct pipe_ctx *otg_master)
{
struct pipe_ctx *opp_heads[MAX_PIPES];
int odm_cnt = 1;
int i;
odm_cnt = resource_get_opp_heads_for_otg_master(otg_master, res_ctx, opp_heads);
/* For ODM slices after the first slice, extra left edge pixel is required
* for 3-tap chroma subsampling.
*/
if (otg_master->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422 ||
otg_master->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
for (i = 0; i < odm_cnt; i++)
opp_heads[i]->stream_res.left_edge_extra_pixel = (i == 0) ? false : true;
}
}
bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
{
const struct dc_plane_state *plane_state = pipe_ctx->plane_state;

10
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
View File

@ -1579,11 +1579,6 @@ static void dcn20_detect_pipe_changes(struct dc_state *old_state,
if (old_pipe->stream_res.tg != new_pipe->stream_res.tg)
new_pipe->update_flags.bits.tg_changed = 1;
if (resource_is_pipe_type(new_pipe, OPP_HEAD)) {
if (old_pipe->stream_res.left_edge_extra_pixel != new_pipe->stream_res.left_edge_extra_pixel)
new_pipe->update_flags.bits.opp_changed = 1;
}
/*
* Detect mpcc blending changes, only dpp inst and opp matter here,
* mpccs getting removed/inserted update connected ones during their own
@ -1967,11 +1962,6 @@ static void dcn20_program_pipe(
pipe_ctx->stream_res.opp,
&pipe_ctx->stream->bit_depth_params,
&pipe_ctx->stream->clamping);
if (resource_is_pipe_type(pipe_ctx, OPP_HEAD))
pipe_ctx->stream_res.opp->funcs->opp_program_left_edge_extra_pixel(
pipe_ctx->stream_res.opp,
pipe_ctx->stream_res.left_edge_extra_pixel);
}
/* Set ABM pipe after other pipe configurations done */

2
drivers/gpu/drm/amd/display/dc/inc/core_types.h
View File

@ -333,8 +333,6 @@ struct stream_resource {
uint8_t gsl_group;
struct test_pattern_params test_pattern_params;
bool left_edge_extra_pixel;
};
struct plane_resource {

4
drivers/gpu/drm/amd/display/dc/inc/resource.h
View File

@ -107,10 +107,6 @@ void resource_build_test_pattern_params(
struct resource_context *res_ctx,
struct pipe_ctx *pipe_ctx);
void resource_build_subsampling_params(
struct resource_context *res_ctx,
struct pipe_ctx *pipe_ctx);
bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx);
enum dc_status resource_build_scaling_params_for_context(