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Merge patch series "scsi: ufs: renesas: Add support for R-Car S4-8 ES1.2"
Geert Uytterhoeven <geert+renesas@glider.be> says:
Hi all,
Initialization of the UFS controller on R-Car S4-8 ES1.0 requires only
static values. However, other UFS controller variants (R-Car S4-8 ES 1.2)
require dynamic values, like those obtained from E-FUSE, and downloading
firmware.
Hence this patch series refactors the initialization code to prepare for
this, and adds support for the UFS controller on R-Car S4-8 ES1.2.
The accompanying DTS change is available at [1].
This has been tested on:
- Renesas Spider with R-Car S4-8 ES1.0 (broken before/after),
- Renesas S4 Starter Kit with R-Car S4-8 ES1.2 (works after).
Thanks for your comments!
[1] "[PATCH] arm64: dts: renesas: r8a779f4: Add UFS tuning parameters in
E-FUSE"
https://lore.kernel.org/3e4fca228eb049d54a1ae520104558505dbdf803.1741179629.git.geert+renesas@glider.be
[2] "[PATCH v2 0/5] scsi: ufs: renesas: Refactor code for other UFS
controller"
https://lore.kernel.org/20240709023550.1750333-1-yoshihiro.shimoda.uh@renesas.com
[3] "[PATCH 0/5] scsi: ufs: renesas: Refactor code for other UFS
controller"
https://lore.kernel.org/20240708120931.1703956-1-yoshihiro.shimoda.uh@renesas.com
Link: https://lore.kernel.org/r/cover.1741179611.git.geert+renesas@glider.be
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Martin K. Petersen
commit
ffd6c17928
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|
@ -33,6 +33,16 @@ properties:
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|||
resets:
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maxItems: 1
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nvmem-cells:
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maxItems: 1
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nvmem-cell-names:
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items:
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- const: calibration
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dependencies:
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nvmem-cells: [ nvmem-cell-names ]
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required:
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- compatible
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- reg
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@ -58,4 +68,6 @@ examples:
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freq-table-hz = <200000000 200000000>, <38400000 38400000>;
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power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
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resets = <&cpg 1514>;
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nvmem-cells = <&ufs_tune>;
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nvmem-cell-names = "calibration";
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};
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|
|
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@ -9,324 +9,408 @@
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/firmware.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/nvmem-consumer.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/sys_soc.h>
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#include <ufs/ufshcd.h>
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#include "ufshcd-pltfrm.h"
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#define EFUSE_CALIB_SIZE 8
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struct ufs_renesas_priv {
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const struct firmware *fw;
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void (*pre_init)(struct ufs_hba *hba);
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bool initialized; /* The hardware needs initialization once */
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u8 calib[EFUSE_CALIB_SIZE];
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};
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enum {
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SET_PHY_INDEX_LO = 0,
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SET_PHY_INDEX_HI,
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TIMER_INDEX,
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MAX_INDEX
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};
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enum ufs_renesas_init_param_mode {
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MODE_RESTORE,
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MODE_SET,
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MODE_SAVE,
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MODE_POLL,
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MODE_WAIT,
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MODE_WRITE,
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};
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#define PARAM_RESTORE(_reg, _index) \
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{ .mode = MODE_RESTORE, .reg = _reg, .index = _index }
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#define PARAM_SET(_index, _set) \
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{ .mode = MODE_SET, .index = _index, .u.set = _set }
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#define PARAM_SAVE(_reg, _mask, _index) \
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{ .mode = MODE_SAVE, .reg = _reg, .mask = (u32)(_mask), \
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.index = _index }
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#define PARAM_POLL(_reg, _expected, _mask) \
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{ .mode = MODE_POLL, .reg = _reg, .u.expected = _expected, \
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.mask = (u32)(_mask) }
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#define PARAM_WAIT(_delay_us) \
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{ .mode = MODE_WAIT, .u.delay_us = _delay_us }
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#define PARAM_WRITE(_reg, _val) \
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{ .mode = MODE_WRITE, .reg = _reg, .u.val = _val }
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#define PARAM_WRITE_D0_D4(_d0, _d4) \
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PARAM_WRITE(0xd0, _d0), PARAM_WRITE(0xd4, _d4)
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#define PARAM_WRITE_800_80C_POLL(_addr, _data_800) \
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PARAM_WRITE_D0_D4(0x0000080c, 0x00000100), \
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PARAM_WRITE_D0_D4(0x00000800, ((_data_800) << 16) | BIT(8) | (_addr)), \
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PARAM_WRITE(0xd0, 0x0000080c), \
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PARAM_POLL(0xd4, BIT(8), BIT(8))
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#define PARAM_RESTORE_800_80C_POLL(_index) \
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PARAM_WRITE_D0_D4(0x0000080c, 0x00000100), \
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PARAM_WRITE(0xd0, 0x00000800), \
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PARAM_RESTORE(0xd4, _index), \
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PARAM_WRITE(0xd0, 0x0000080c), \
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PARAM_POLL(0xd4, BIT(8), BIT(8))
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#define PARAM_WRITE_804_80C_POLL(_addr, _data_804) \
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PARAM_WRITE_D0_D4(0x0000080c, 0x00000100), \
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PARAM_WRITE_D0_D4(0x00000804, ((_data_804) << 16) | BIT(8) | (_addr)), \
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PARAM_WRITE(0xd0, 0x0000080c), \
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PARAM_POLL(0xd4, BIT(8), BIT(8))
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#define PARAM_WRITE_828_82C_POLL(_data_828) \
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PARAM_WRITE_D0_D4(0x0000082c, 0x0f000000), \
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PARAM_WRITE_D0_D4(0x00000828, _data_828), \
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PARAM_WRITE(0xd0, 0x0000082c), \
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PARAM_POLL(0xd4, _data_828, _data_828)
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#define PARAM_WRITE_PHY(_addr16, _data16) \
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PARAM_WRITE(0xf0, 1), \
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PARAM_WRITE_800_80C_POLL(0x16, (_addr16) & 0xff), \
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PARAM_WRITE_800_80C_POLL(0x17, ((_addr16) >> 8) & 0xff), \
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PARAM_WRITE_800_80C_POLL(0x18, (_data16) & 0xff), \
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PARAM_WRITE_800_80C_POLL(0x19, ((_data16) >> 8) & 0xff), \
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PARAM_WRITE_800_80C_POLL(0x1c, 0x01), \
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PARAM_WRITE_828_82C_POLL(0x0f000000), \
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PARAM_WRITE(0xf0, 0)
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#define PARAM_SET_PHY(_addr16, _data16) \
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PARAM_WRITE(0xf0, 1), \
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PARAM_WRITE_800_80C_POLL(0x16, (_addr16) & 0xff), \
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PARAM_WRITE_800_80C_POLL(0x17, ((_addr16) >> 8) & 0xff), \
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PARAM_WRITE_800_80C_POLL(0x1c, 0x01), \
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PARAM_WRITE_828_82C_POLL(0x0f000000), \
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PARAM_WRITE_804_80C_POLL(0x1a, 0), \
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PARAM_WRITE(0xd0, 0x00000808), \
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PARAM_SAVE(0xd4, 0xff, SET_PHY_INDEX_LO), \
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PARAM_WRITE_804_80C_POLL(0x1b, 0), \
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PARAM_WRITE(0xd0, 0x00000808), \
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PARAM_SAVE(0xd4, 0xff, SET_PHY_INDEX_HI), \
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PARAM_WRITE_828_82C_POLL(0x0f000000), \
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PARAM_WRITE(0xf0, 0), \
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PARAM_WRITE(0xf0, 1), \
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PARAM_WRITE_800_80C_POLL(0x16, (_addr16) & 0xff), \
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PARAM_WRITE_800_80C_POLL(0x17, ((_addr16) >> 8) & 0xff), \
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PARAM_SET(SET_PHY_INDEX_LO, ((_data16 & 0xff) << 16) | BIT(8) | 0x18), \
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PARAM_RESTORE_800_80C_POLL(SET_PHY_INDEX_LO), \
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PARAM_SET(SET_PHY_INDEX_HI, (((_data16 >> 8) & 0xff) << 16) | BIT(8) | 0x19), \
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PARAM_RESTORE_800_80C_POLL(SET_PHY_INDEX_HI), \
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PARAM_WRITE_800_80C_POLL(0x1c, 0x01), \
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PARAM_WRITE_828_82C_POLL(0x0f000000), \
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PARAM_WRITE(0xf0, 0)
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#define PARAM_INDIRECT_WRITE(_gpio, _addr, _data_800) \
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PARAM_WRITE(0xf0, _gpio), \
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PARAM_WRITE_800_80C_POLL(_addr, _data_800), \
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PARAM_WRITE_828_82C_POLL(0x0f000000), \
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PARAM_WRITE(0xf0, 0)
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#define PARAM_INDIRECT_POLL(_gpio, _addr, _expected, _mask) \
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PARAM_WRITE(0xf0, _gpio), \
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PARAM_WRITE_800_80C_POLL(_addr, 0), \
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PARAM_WRITE(0xd0, 0x00000808), \
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PARAM_POLL(0xd4, _expected, _mask), \
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PARAM_WRITE(0xf0, 0)
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struct ufs_renesas_init_param {
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enum ufs_renesas_init_param_mode mode;
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u32 reg;
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union {
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u32 expected;
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u32 delay_us;
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u32 set;
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u32 val;
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} u;
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u32 mask;
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u32 index;
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};
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/* This setting is for SERIES B */
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static const struct ufs_renesas_init_param ufs_param[] = {
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PARAM_WRITE(0xc0, 0x49425308),
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PARAM_WRITE_D0_D4(0x00000104, 0x00000002),
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PARAM_WAIT(1),
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PARAM_WRITE_D0_D4(0x00000828, 0x00000200),
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PARAM_WAIT(1),
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PARAM_WRITE_D0_D4(0x00000828, 0x00000000),
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PARAM_WRITE_D0_D4(0x00000104, 0x00000001),
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PARAM_WRITE_D0_D4(0x00000940, 0x00000001),
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PARAM_WAIT(1),
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PARAM_WRITE_D0_D4(0x00000940, 0x00000000),
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PARAM_WRITE(0xc0, 0x49425308),
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PARAM_WRITE(0xc0, 0x41584901),
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PARAM_WRITE_D0_D4(0x0000080c, 0x00000100),
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PARAM_WRITE_D0_D4(0x00000804, 0x00000000),
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PARAM_WRITE(0xd0, 0x0000080c),
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PARAM_POLL(0xd4, BIT(8), BIT(8)),
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PARAM_WRITE(REG_CONTROLLER_ENABLE, 0x00000001),
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PARAM_WRITE(0xd0, 0x00000804),
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PARAM_POLL(0xd4, BIT(8) | BIT(6) | BIT(0), BIT(8) | BIT(6) | BIT(0)),
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PARAM_WRITE(0xd0, 0x00000d00),
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PARAM_SAVE(0xd4, 0x0000ffff, TIMER_INDEX),
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PARAM_WRITE(0xd4, 0x00000000),
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PARAM_WRITE_D0_D4(0x0000082c, 0x0f000000),
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PARAM_WRITE_D0_D4(0x00000828, 0x08000000),
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PARAM_WRITE(0xd0, 0x0000082c),
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PARAM_POLL(0xd4, BIT(27), BIT(27)),
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PARAM_WRITE(0xd0, 0x00000d2c),
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PARAM_POLL(0xd4, BIT(0), BIT(0)),
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/* phy setup */
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PARAM_INDIRECT_WRITE(1, 0x01, 0x001f),
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PARAM_INDIRECT_WRITE(7, 0x5d, 0x0014),
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PARAM_INDIRECT_WRITE(7, 0x5e, 0x0014),
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PARAM_INDIRECT_WRITE(7, 0x0d, 0x0003),
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PARAM_INDIRECT_WRITE(7, 0x0e, 0x0007),
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PARAM_INDIRECT_WRITE(7, 0x5f, 0x0003),
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PARAM_INDIRECT_WRITE(7, 0x60, 0x0003),
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PARAM_INDIRECT_WRITE(7, 0x5b, 0x00a6),
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PARAM_INDIRECT_WRITE(7, 0x5c, 0x0003),
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PARAM_INDIRECT_POLL(7, 0x3c, 0, BIT(7)),
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PARAM_INDIRECT_POLL(7, 0x4c, 0, BIT(4)),
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PARAM_INDIRECT_WRITE(1, 0x32, 0x0080),
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PARAM_INDIRECT_WRITE(1, 0x1f, 0x0001),
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PARAM_INDIRECT_WRITE(0, 0x2c, 0x0001),
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PARAM_INDIRECT_WRITE(0, 0x32, 0x0087),
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PARAM_INDIRECT_WRITE(1, 0x4d, 0x0061),
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PARAM_INDIRECT_WRITE(4, 0x9b, 0x0009),
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PARAM_INDIRECT_WRITE(4, 0xa6, 0x0005),
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PARAM_INDIRECT_WRITE(4, 0xa5, 0x0058),
|
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PARAM_INDIRECT_WRITE(1, 0x39, 0x0027),
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PARAM_INDIRECT_WRITE(1, 0x47, 0x004c),
|
||||
|
||||
PARAM_INDIRECT_WRITE(7, 0x0d, 0x0002),
|
||||
PARAM_INDIRECT_WRITE(7, 0x0e, 0x0007),
|
||||
|
||||
PARAM_WRITE_PHY(0x0028, 0x0061),
|
||||
PARAM_WRITE_PHY(0x4014, 0x0061),
|
||||
PARAM_SET_PHY(0x401c, BIT(2)),
|
||||
PARAM_WRITE_PHY(0x4000, 0x0000),
|
||||
PARAM_WRITE_PHY(0x4001, 0x0000),
|
||||
|
||||
PARAM_WRITE_PHY(0x10ae, 0x0001),
|
||||
PARAM_WRITE_PHY(0x10ad, 0x0000),
|
||||
PARAM_WRITE_PHY(0x10af, 0x0001),
|
||||
PARAM_WRITE_PHY(0x10b6, 0x0001),
|
||||
PARAM_WRITE_PHY(0x10ae, 0x0000),
|
||||
|
||||
PARAM_WRITE_PHY(0x10ae, 0x0001),
|
||||
PARAM_WRITE_PHY(0x10ad, 0x0000),
|
||||
PARAM_WRITE_PHY(0x10af, 0x0002),
|
||||
PARAM_WRITE_PHY(0x10b6, 0x0001),
|
||||
PARAM_WRITE_PHY(0x10ae, 0x0000),
|
||||
|
||||
PARAM_WRITE_PHY(0x10ae, 0x0001),
|
||||
PARAM_WRITE_PHY(0x10ad, 0x0080),
|
||||
PARAM_WRITE_PHY(0x10af, 0x0000),
|
||||
PARAM_WRITE_PHY(0x10b6, 0x0001),
|
||||
PARAM_WRITE_PHY(0x10ae, 0x0000),
|
||||
|
||||
PARAM_WRITE_PHY(0x10ae, 0x0001),
|
||||
PARAM_WRITE_PHY(0x10ad, 0x0080),
|
||||
PARAM_WRITE_PHY(0x10af, 0x001a),
|
||||
PARAM_WRITE_PHY(0x10b6, 0x0001),
|
||||
PARAM_WRITE_PHY(0x10ae, 0x0000),
|
||||
|
||||
PARAM_INDIRECT_WRITE(7, 0x70, 0x0016),
|
||||
PARAM_INDIRECT_WRITE(7, 0x71, 0x0016),
|
||||
PARAM_INDIRECT_WRITE(7, 0x72, 0x0014),
|
||||
PARAM_INDIRECT_WRITE(7, 0x73, 0x0014),
|
||||
PARAM_INDIRECT_WRITE(7, 0x74, 0x0000),
|
||||
PARAM_INDIRECT_WRITE(7, 0x75, 0x0000),
|
||||
PARAM_INDIRECT_WRITE(7, 0x76, 0x0010),
|
||||
PARAM_INDIRECT_WRITE(7, 0x77, 0x0010),
|
||||
PARAM_INDIRECT_WRITE(7, 0x78, 0x00ff),
|
||||
PARAM_INDIRECT_WRITE(7, 0x79, 0x0000),
|
||||
|
||||
PARAM_INDIRECT_WRITE(7, 0x19, 0x0007),
|
||||
|
||||
PARAM_INDIRECT_WRITE(7, 0x1a, 0x0007),
|
||||
|
||||
PARAM_INDIRECT_WRITE(7, 0x24, 0x000c),
|
||||
|
||||
PARAM_INDIRECT_WRITE(7, 0x25, 0x000c),
|
||||
|
||||
PARAM_INDIRECT_WRITE(7, 0x62, 0x0000),
|
||||
PARAM_INDIRECT_WRITE(7, 0x63, 0x0000),
|
||||
PARAM_INDIRECT_WRITE(7, 0x5d, 0x0014),
|
||||
PARAM_INDIRECT_WRITE(7, 0x5e, 0x0017),
|
||||
PARAM_INDIRECT_WRITE(7, 0x5d, 0x0004),
|
||||
PARAM_INDIRECT_WRITE(7, 0x5e, 0x0017),
|
||||
PARAM_INDIRECT_POLL(7, 0x55, 0, BIT(6)),
|
||||
PARAM_INDIRECT_POLL(7, 0x41, 0, BIT(7)),
|
||||
/* end of phy setup */
|
||||
|
||||
PARAM_WRITE(0xf0, 0),
|
||||
PARAM_WRITE(0xd0, 0x00000d00),
|
||||
PARAM_RESTORE(0xd4, TIMER_INDEX),
|
||||
};
|
||||
#define UFS_RENESAS_FIRMWARE_NAME "r8a779f0_ufs.bin"
|
||||
MODULE_FIRMWARE(UFS_RENESAS_FIRMWARE_NAME);
|
||||
|
||||
static void ufs_renesas_dbg_register_dump(struct ufs_hba *hba)
|
||||
{
|
||||
ufshcd_dump_regs(hba, 0xc0, 0x40, "regs: 0xc0 + ");
|
||||
}
|
||||
|
||||
static void ufs_renesas_reg_control(struct ufs_hba *hba,
|
||||
const struct ufs_renesas_init_param *p)
|
||||
static void ufs_renesas_poll(struct ufs_hba *hba, u32 reg, u32 expected, u32 mask)
|
||||
{
|
||||
static u32 save[MAX_INDEX];
|
||||
int ret;
|
||||
u32 val;
|
||||
|
||||
WARN_ON(p->index >= MAX_INDEX);
|
||||
|
||||
switch (p->mode) {
|
||||
case MODE_RESTORE:
|
||||
ufshcd_writel(hba, save[p->index], p->reg);
|
||||
break;
|
||||
case MODE_SET:
|
||||
save[p->index] |= p->u.set;
|
||||
break;
|
||||
case MODE_SAVE:
|
||||
save[p->index] = ufshcd_readl(hba, p->reg) & p->mask;
|
||||
break;
|
||||
case MODE_POLL:
|
||||
ret = readl_poll_timeout_atomic(hba->mmio_base + p->reg,
|
||||
val,
|
||||
(val & p->mask) == p->u.expected,
|
||||
10, 1000);
|
||||
if (ret)
|
||||
dev_err(hba->dev, "%s: poll failed %d (%08x, %08x, %08x)\n",
|
||||
__func__, ret, val, p->mask, p->u.expected);
|
||||
break;
|
||||
case MODE_WAIT:
|
||||
if (p->u.delay_us > 1000)
|
||||
mdelay(DIV_ROUND_UP(p->u.delay_us, 1000));
|
||||
else
|
||||
udelay(p->u.delay_us);
|
||||
break;
|
||||
case MODE_WRITE:
|
||||
ufshcd_writel(hba, p->u.val, p->reg);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
ret = readl_poll_timeout_atomic(hba->mmio_base + reg,
|
||||
val, (val & mask) == expected,
|
||||
10, 1000);
|
||||
if (ret)
|
||||
dev_err(hba->dev, "%s: poll failed %d (%08x, %08x, %08x)\n",
|
||||
__func__, ret, val, mask, expected);
|
||||
}
|
||||
|
||||
static void ufs_renesas_pre_init(struct ufs_hba *hba)
|
||||
static u32 ufs_renesas_read(struct ufs_hba *hba, u32 reg)
|
||||
{
|
||||
const struct ufs_renesas_init_param *p = ufs_param;
|
||||
unsigned int i;
|
||||
return ufshcd_readl(hba, reg);
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(ufs_param); i++)
|
||||
ufs_renesas_reg_control(hba, &p[i]);
|
||||
static void ufs_renesas_write(struct ufs_hba *hba, u32 reg, u32 value)
|
||||
{
|
||||
ufshcd_writel(hba, value, reg);
|
||||
}
|
||||
|
||||
static void ufs_renesas_write_d0_d4(struct ufs_hba *hba, u32 data_d0, u32 data_d4)
|
||||
{
|
||||
ufs_renesas_write(hba, 0xd0, data_d0);
|
||||
ufs_renesas_write(hba, 0xd4, data_d4);
|
||||
}
|
||||
|
||||
static void ufs_renesas_write_800_80c_poll(struct ufs_hba *hba, u32 addr,
|
||||
u32 data_800)
|
||||
{
|
||||
ufs_renesas_write_d0_d4(hba, 0x0000080c, 0x00000100);
|
||||
ufs_renesas_write_d0_d4(hba, 0x00000800, (data_800 << 16) | BIT(8) | addr);
|
||||
ufs_renesas_write(hba, 0xd0, 0x0000080c);
|
||||
ufs_renesas_poll(hba, 0xd4, BIT(8), BIT(8));
|
||||
}
|
||||
|
||||
static void ufs_renesas_write_804_80c_poll(struct ufs_hba *hba, u32 addr, u32 data_804)
|
||||
{
|
||||
ufs_renesas_write_d0_d4(hba, 0x0000080c, 0x00000100);
|
||||
ufs_renesas_write_d0_d4(hba, 0x00000804, (data_804 << 16) | BIT(8) | addr);
|
||||
ufs_renesas_write(hba, 0xd0, 0x0000080c);
|
||||
ufs_renesas_poll(hba, 0xd4, BIT(8), BIT(8));
|
||||
}
|
||||
|
||||
static void ufs_renesas_write_828_82c_poll(struct ufs_hba *hba, u32 data_828)
|
||||
{
|
||||
ufs_renesas_write_d0_d4(hba, 0x0000082c, 0x0f000000);
|
||||
ufs_renesas_write_d0_d4(hba, 0x00000828, data_828);
|
||||
ufs_renesas_write(hba, 0xd0, 0x0000082c);
|
||||
ufs_renesas_poll(hba, 0xd4, data_828, data_828);
|
||||
}
|
||||
|
||||
static void ufs_renesas_write_phy(struct ufs_hba *hba, u32 addr16, u32 data16)
|
||||
{
|
||||
ufs_renesas_write(hba, 0xf0, 1);
|
||||
ufs_renesas_write_800_80c_poll(hba, 0x16, addr16 & 0xff);
|
||||
ufs_renesas_write_800_80c_poll(hba, 0x17, (addr16 >> 8) & 0xff);
|
||||
ufs_renesas_write_800_80c_poll(hba, 0x18, data16 & 0xff);
|
||||
ufs_renesas_write_800_80c_poll(hba, 0x19, (data16 >> 8) & 0xff);
|
||||
ufs_renesas_write_800_80c_poll(hba, 0x1c, 0x01);
|
||||
ufs_renesas_write_828_82c_poll(hba, 0x0f000000);
|
||||
ufs_renesas_write(hba, 0xf0, 0);
|
||||
}
|
||||
|
||||
static void ufs_renesas_set_phy(struct ufs_hba *hba, u32 addr16, u32 data16)
|
||||
{
|
||||
u32 low, high;
|
||||
|
||||
ufs_renesas_write(hba, 0xf0, 1);
|
||||
ufs_renesas_write_800_80c_poll(hba, 0x16, addr16 & 0xff);
|
||||
ufs_renesas_write_800_80c_poll(hba, 0x17, (addr16 >> 8) & 0xff);
|
||||
ufs_renesas_write_800_80c_poll(hba, 0x1c, 0x01);
|
||||
ufs_renesas_write_828_82c_poll(hba, 0x0f000000);
|
||||
ufs_renesas_write_804_80c_poll(hba, 0x1a, 0);
|
||||
ufs_renesas_write(hba, 0xd0, 0x00000808);
|
||||
low = ufs_renesas_read(hba, 0xd4) & 0xff;
|
||||
ufs_renesas_write_804_80c_poll(hba, 0x1b, 0);
|
||||
ufs_renesas_write(hba, 0xd0, 0x00000808);
|
||||
high = ufs_renesas_read(hba, 0xd4) & 0xff;
|
||||
ufs_renesas_write_828_82c_poll(hba, 0x0f000000);
|
||||
ufs_renesas_write(hba, 0xf0, 0);
|
||||
|
||||
data16 |= (high << 8) | low;
|
||||
ufs_renesas_write_phy(hba, addr16, data16);
|
||||
}
|
||||
|
||||
static void ufs_renesas_reset_indirect_write(struct ufs_hba *hba, int gpio,
|
||||
u32 addr, u32 data)
|
||||
{
|
||||
ufs_renesas_write(hba, 0xf0, gpio);
|
||||
ufs_renesas_write_800_80c_poll(hba, addr, data);
|
||||
}
|
||||
|
||||
static void ufs_renesas_reset_indirect_update(struct ufs_hba *hba)
|
||||
{
|
||||
ufs_renesas_write_d0_d4(hba, 0x0000082c, 0x0f000000);
|
||||
ufs_renesas_write_d0_d4(hba, 0x00000828, 0x0f000000);
|
||||
ufs_renesas_write(hba, 0xd0, 0x0000082c);
|
||||
ufs_renesas_poll(hba, 0xd4, BIT(27) | BIT(26) | BIT(24), BIT(27) | BIT(26) | BIT(24));
|
||||
ufs_renesas_write(hba, 0xf0, 0);
|
||||
}
|
||||
|
||||
static void ufs_renesas_indirect_write(struct ufs_hba *hba, u32 gpio, u32 addr,
|
||||
u32 data_800)
|
||||
{
|
||||
ufs_renesas_write(hba, 0xf0, gpio);
|
||||
ufs_renesas_write_800_80c_poll(hba, addr, data_800);
|
||||
ufs_renesas_write_828_82c_poll(hba, 0x0f000000);
|
||||
ufs_renesas_write(hba, 0xf0, 0);
|
||||
}
|
||||
|
||||
static void ufs_renesas_indirect_poll(struct ufs_hba *hba, u32 gpio, u32 addr,
|
||||
u32 expected, u32 mask)
|
||||
{
|
||||
ufs_renesas_write(hba, 0xf0, gpio);
|
||||
ufs_renesas_write_800_80c_poll(hba, addr, 0);
|
||||
ufs_renesas_write(hba, 0xd0, 0x00000808);
|
||||
ufs_renesas_poll(hba, 0xd4, expected, mask);
|
||||
ufs_renesas_write(hba, 0xf0, 0);
|
||||
}
|
||||
|
||||
static void ufs_renesas_init_step1_to_3(struct ufs_hba *hba, bool init108)
|
||||
{
|
||||
ufs_renesas_write(hba, 0xc0, 0x49425308);
|
||||
ufs_renesas_write_d0_d4(hba, 0x00000104, 0x00000002);
|
||||
if (init108)
|
||||
ufs_renesas_write_d0_d4(hba, 0x00000108, 0x00000002);
|
||||
udelay(1);
|
||||
ufs_renesas_write_d0_d4(hba, 0x00000828, 0x00000200);
|
||||
udelay(1);
|
||||
ufs_renesas_write_d0_d4(hba, 0x00000828, 0x00000000);
|
||||
ufs_renesas_write_d0_d4(hba, 0x00000104, 0x00000001);
|
||||
if (init108)
|
||||
ufs_renesas_write_d0_d4(hba, 0x00000108, 0x00000001);
|
||||
ufs_renesas_write_d0_d4(hba, 0x00000940, 0x00000001);
|
||||
udelay(1);
|
||||
ufs_renesas_write_d0_d4(hba, 0x00000940, 0x00000000);
|
||||
|
||||
ufs_renesas_write(hba, 0xc0, 0x49425308);
|
||||
ufs_renesas_write(hba, 0xc0, 0x41584901);
|
||||
}
|
||||
|
||||
static void ufs_renesas_init_step4_to_6(struct ufs_hba *hba)
|
||||
{
|
||||
ufs_renesas_write_d0_d4(hba, 0x0000080c, 0x00000100);
|
||||
ufs_renesas_write_d0_d4(hba, 0x00000804, 0x00000000);
|
||||
ufs_renesas_write(hba, 0xd0, 0x0000080c);
|
||||
ufs_renesas_poll(hba, 0xd4, BIT(8), BIT(8));
|
||||
|
||||
ufs_renesas_write(hba, REG_CONTROLLER_ENABLE, 0x00000001);
|
||||
|
||||
ufs_renesas_write(hba, 0xd0, 0x00000804);
|
||||
ufs_renesas_poll(hba, 0xd4, BIT(8) | BIT(6) | BIT(0), BIT(8) | BIT(6) | BIT(0));
|
||||
}
|
||||
|
||||
static u32 ufs_renesas_init_disable_timer(struct ufs_hba *hba)
|
||||
{
|
||||
u32 timer_val;
|
||||
|
||||
ufs_renesas_write(hba, 0xd0, 0x00000d00);
|
||||
timer_val = ufs_renesas_read(hba, 0xd4) & 0x0000ffff;
|
||||
ufs_renesas_write(hba, 0xd4, 0x00000000);
|
||||
ufs_renesas_write_d0_d4(hba, 0x0000082c, 0x0f000000);
|
||||
ufs_renesas_write_d0_d4(hba, 0x00000828, 0x08000000);
|
||||
ufs_renesas_write(hba, 0xd0, 0x0000082c);
|
||||
ufs_renesas_poll(hba, 0xd4, BIT(27), BIT(27));
|
||||
ufs_renesas_write(hba, 0xd0, 0x00000d2c);
|
||||
ufs_renesas_poll(hba, 0xd4, BIT(0), BIT(0));
|
||||
|
||||
return timer_val;
|
||||
}
|
||||
|
||||
static void ufs_renesas_init_enable_timer(struct ufs_hba *hba, u32 timer_val)
|
||||
{
|
||||
ufs_renesas_write(hba, 0xf0, 0);
|
||||
ufs_renesas_write(hba, 0xd0, 0x00000d00);
|
||||
ufs_renesas_write(hba, 0xd4, timer_val);
|
||||
}
|
||||
|
||||
static void ufs_renesas_write_phy_10ad_10af(struct ufs_hba *hba,
|
||||
u32 data_10ad, u32 data_10af)
|
||||
{
|
||||
ufs_renesas_write_phy(hba, 0x10ae, 0x0001);
|
||||
ufs_renesas_write_phy(hba, 0x10ad, data_10ad);
|
||||
ufs_renesas_write_phy(hba, 0x10af, data_10af);
|
||||
ufs_renesas_write_phy(hba, 0x10b6, 0x0001);
|
||||
ufs_renesas_write_phy(hba, 0x10ae, 0x0000);
|
||||
}
|
||||
|
||||
static void ufs_renesas_init_compensation_and_slicers(struct ufs_hba *hba)
|
||||
{
|
||||
ufs_renesas_write_phy_10ad_10af(hba, 0x0000, 0x0001);
|
||||
ufs_renesas_write_phy_10ad_10af(hba, 0x0000, 0x0002);
|
||||
ufs_renesas_write_phy_10ad_10af(hba, 0x0080, 0x0000);
|
||||
ufs_renesas_write_phy_10ad_10af(hba, 0x0080, 0x001a);
|
||||
}
|
||||
|
||||
static void ufs_renesas_r8a779f0_es10_pre_init(struct ufs_hba *hba)
|
||||
{
|
||||
u32 timer_val;
|
||||
|
||||
/* This setting is for SERIES B */
|
||||
ufs_renesas_init_step1_to_3(hba, false);
|
||||
|
||||
ufs_renesas_init_step4_to_6(hba);
|
||||
|
||||
timer_val = ufs_renesas_init_disable_timer(hba);
|
||||
|
||||
/* phy setup */
|
||||
ufs_renesas_indirect_write(hba, 1, 0x01, 0x001f);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0014);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0014);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x0d, 0x0003);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x0e, 0x0007);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x5f, 0x0003);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x60, 0x0003);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x5b, 0x00a6);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x5c, 0x0003);
|
||||
|
||||
ufs_renesas_indirect_poll(hba, 7, 0x3c, 0, BIT(7));
|
||||
ufs_renesas_indirect_poll(hba, 7, 0x4c, 0, BIT(4));
|
||||
|
||||
ufs_renesas_indirect_write(hba, 1, 0x32, 0x0080);
|
||||
ufs_renesas_indirect_write(hba, 1, 0x1f, 0x0001);
|
||||
ufs_renesas_indirect_write(hba, 0, 0x2c, 0x0001);
|
||||
ufs_renesas_indirect_write(hba, 0, 0x32, 0x0087);
|
||||
|
||||
ufs_renesas_indirect_write(hba, 1, 0x4d, 0x0061);
|
||||
ufs_renesas_indirect_write(hba, 4, 0x9b, 0x0009);
|
||||
ufs_renesas_indirect_write(hba, 4, 0xa6, 0x0005);
|
||||
ufs_renesas_indirect_write(hba, 4, 0xa5, 0x0058);
|
||||
ufs_renesas_indirect_write(hba, 1, 0x39, 0x0027);
|
||||
ufs_renesas_indirect_write(hba, 1, 0x47, 0x004c);
|
||||
|
||||
ufs_renesas_indirect_write(hba, 7, 0x0d, 0x0002);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x0e, 0x0007);
|
||||
|
||||
ufs_renesas_write_phy(hba, 0x0028, 0x0061);
|
||||
ufs_renesas_write_phy(hba, 0x4014, 0x0061);
|
||||
ufs_renesas_set_phy(hba, 0x401c, BIT(2));
|
||||
ufs_renesas_write_phy(hba, 0x4000, 0x0000);
|
||||
ufs_renesas_write_phy(hba, 0x4001, 0x0000);
|
||||
|
||||
ufs_renesas_init_compensation_and_slicers(hba);
|
||||
|
||||
ufs_renesas_indirect_write(hba, 7, 0x70, 0x0016);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x71, 0x0016);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x72, 0x0014);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x73, 0x0014);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x74, 0x0000);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x75, 0x0000);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x76, 0x0010);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x77, 0x0010);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x78, 0x00ff);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x79, 0x0000);
|
||||
|
||||
ufs_renesas_indirect_write(hba, 7, 0x19, 0x0007);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x1a, 0x0007);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x24, 0x000c);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x25, 0x000c);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x62, 0x0000);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x63, 0x0000);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0014);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0017);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0004);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0017);
|
||||
ufs_renesas_indirect_poll(hba, 7, 0x55, 0, BIT(6));
|
||||
ufs_renesas_indirect_poll(hba, 7, 0x41, 0, BIT(7));
|
||||
/* end of phy setup */
|
||||
|
||||
ufs_renesas_init_enable_timer(hba, timer_val);
|
||||
}
|
||||
|
||||
static void ufs_renesas_r8a779f0_init_step3_add(struct ufs_hba *hba, bool assert)
|
||||
{
|
||||
u32 val_2x = 0, val_3x = 0, val_4x = 0;
|
||||
|
||||
if (assert) {
|
||||
val_2x = 0x0001;
|
||||
val_3x = 0x0003;
|
||||
val_4x = 0x0001;
|
||||
}
|
||||
|
||||
ufs_renesas_reset_indirect_write(hba, 7, 0x20, val_2x);
|
||||
ufs_renesas_reset_indirect_write(hba, 7, 0x4a, val_4x);
|
||||
ufs_renesas_reset_indirect_write(hba, 7, 0x35, val_3x);
|
||||
ufs_renesas_reset_indirect_update(hba);
|
||||
ufs_renesas_reset_indirect_write(hba, 7, 0x21, val_2x);
|
||||
ufs_renesas_reset_indirect_write(hba, 7, 0x4b, val_4x);
|
||||
ufs_renesas_reset_indirect_write(hba, 7, 0x36, val_3x);
|
||||
ufs_renesas_reset_indirect_update(hba);
|
||||
}
|
||||
|
||||
static void ufs_renesas_r8a779f0_pre_init(struct ufs_hba *hba)
|
||||
{
|
||||
struct ufs_renesas_priv *priv = ufshcd_get_variant(hba);
|
||||
u32 timer_val;
|
||||
u32 data;
|
||||
int i;
|
||||
|
||||
/* This setting is for SERIES B */
|
||||
ufs_renesas_init_step1_to_3(hba, true);
|
||||
|
||||
ufs_renesas_r8a779f0_init_step3_add(hba, true);
|
||||
ufs_renesas_reset_indirect_write(hba, 7, 0x5f, 0x0063);
|
||||
ufs_renesas_reset_indirect_update(hba);
|
||||
ufs_renesas_reset_indirect_write(hba, 7, 0x60, 0x0003);
|
||||
ufs_renesas_reset_indirect_update(hba);
|
||||
ufs_renesas_reset_indirect_write(hba, 7, 0x5b, 0x00a6);
|
||||
ufs_renesas_reset_indirect_update(hba);
|
||||
ufs_renesas_reset_indirect_write(hba, 7, 0x5c, 0x0003);
|
||||
ufs_renesas_reset_indirect_update(hba);
|
||||
ufs_renesas_r8a779f0_init_step3_add(hba, false);
|
||||
|
||||
ufs_renesas_init_step4_to_6(hba);
|
||||
|
||||
timer_val = ufs_renesas_init_disable_timer(hba);
|
||||
|
||||
ufs_renesas_indirect_write(hba, 1, 0x01, 0x001f);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0014);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0014);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x0d, 0x0007);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x0e, 0x0007);
|
||||
|
||||
ufs_renesas_indirect_poll(hba, 7, 0x3c, 0, BIT(7));
|
||||
ufs_renesas_indirect_poll(hba, 7, 0x4c, 0, BIT(4));
|
||||
|
||||
ufs_renesas_indirect_write(hba, 1, 0x32, 0x0080);
|
||||
ufs_renesas_indirect_write(hba, 1, 0x1f, 0x0001);
|
||||
ufs_renesas_indirect_write(hba, 1, 0x2c, 0x0001);
|
||||
ufs_renesas_indirect_write(hba, 1, 0x32, 0x0087);
|
||||
|
||||
ufs_renesas_indirect_write(hba, 1, 0x4d, priv->calib[2]);
|
||||
ufs_renesas_indirect_write(hba, 1, 0x4e, priv->calib[3]);
|
||||
ufs_renesas_indirect_write(hba, 1, 0x0d, 0x0006);
|
||||
ufs_renesas_indirect_write(hba, 1, 0x0e, 0x0007);
|
||||
ufs_renesas_write_phy(hba, 0x0028, priv->calib[3]);
|
||||
ufs_renesas_write_phy(hba, 0x4014, priv->calib[3]);
|
||||
|
||||
ufs_renesas_set_phy(hba, 0x401c, BIT(2));
|
||||
|
||||
ufs_renesas_write_phy(hba, 0x4000, priv->calib[6]);
|
||||
ufs_renesas_write_phy(hba, 0x4001, priv->calib[7]);
|
||||
|
||||
ufs_renesas_indirect_write(hba, 1, 0x14, 0x0001);
|
||||
|
||||
ufs_renesas_init_compensation_and_slicers(hba);
|
||||
|
||||
ufs_renesas_indirect_write(hba, 7, 0x79, 0x0000);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x24, 0x000c);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x25, 0x000c);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x62, 0x00c0);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x63, 0x0001);
|
||||
|
||||
for (i = 0; i < priv->fw->size / 2; i++) {
|
||||
data = (priv->fw->data[i * 2 + 1] << 8) | priv->fw->data[i * 2];
|
||||
ufs_renesas_write_phy(hba, 0xc000 + i, data);
|
||||
}
|
||||
|
||||
ufs_renesas_indirect_write(hba, 7, 0x0d, 0x0002);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x0e, 0x0007);
|
||||
|
||||
ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0014);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0017);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x5d, 0x0004);
|
||||
ufs_renesas_indirect_write(hba, 7, 0x5e, 0x0017);
|
||||
ufs_renesas_indirect_poll(hba, 7, 0x55, 0, BIT(6));
|
||||
ufs_renesas_indirect_poll(hba, 7, 0x41, 0, BIT(7));
|
||||
|
||||
ufs_renesas_init_enable_timer(hba, timer_val);
|
||||
}
|
||||
|
||||
static int ufs_renesas_hce_enable_notify(struct ufs_hba *hba,
|
||||
|
|
@ -338,7 +422,7 @@ static int ufs_renesas_hce_enable_notify(struct ufs_hba *hba,
|
|||
return 0;
|
||||
|
||||
if (status == PRE_CHANGE)
|
||||
ufs_renesas_pre_init(hba);
|
||||
priv->pre_init(hba);
|
||||
|
||||
priv->initialized = true;
|
||||
|
||||
|
|
@ -356,20 +440,78 @@ static int ufs_renesas_setup_clocks(struct ufs_hba *hba, bool on,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static const struct soc_device_attribute ufs_fallback[] = {
|
||||
{ .soc_id = "r8a779f0", .revision = "ES1.[01]" },
|
||||
{ /* Sentinel */ }
|
||||
};
|
||||
|
||||
static int ufs_renesas_init(struct ufs_hba *hba)
|
||||
{
|
||||
const struct soc_device_attribute *attr;
|
||||
struct nvmem_cell *cell = NULL;
|
||||
struct device *dev = hba->dev;
|
||||
struct ufs_renesas_priv *priv;
|
||||
u8 *data = NULL;
|
||||
size_t len;
|
||||
int ret;
|
||||
|
||||
priv = devm_kzalloc(hba->dev, sizeof(*priv), GFP_KERNEL);
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
ufshcd_set_variant(hba, priv);
|
||||
|
||||
hba->quirks |= UFSHCD_QUIRK_HIBERN_FASTAUTO;
|
||||
|
||||
attr = soc_device_match(ufs_fallback);
|
||||
if (attr)
|
||||
goto fallback;
|
||||
|
||||
ret = request_firmware(&priv->fw, UFS_RENESAS_FIRMWARE_NAME, dev);
|
||||
if (ret) {
|
||||
dev_warn(dev, "Failed to load firmware\n");
|
||||
goto fallback;
|
||||
}
|
||||
|
||||
cell = nvmem_cell_get(dev, "calibration");
|
||||
if (IS_ERR(cell)) {
|
||||
dev_warn(dev, "No calibration data specified\n");
|
||||
goto fallback;
|
||||
}
|
||||
|
||||
data = nvmem_cell_read(cell, &len);
|
||||
if (IS_ERR(data)) {
|
||||
dev_warn(dev, "Failed to read calibration data: %pe\n", data);
|
||||
goto fallback;
|
||||
}
|
||||
|
||||
if (len != EFUSE_CALIB_SIZE) {
|
||||
dev_warn(dev, "Invalid calibration data size %zu\n", len);
|
||||
goto fallback;
|
||||
}
|
||||
|
||||
memcpy(priv->calib, data, EFUSE_CALIB_SIZE);
|
||||
priv->pre_init = ufs_renesas_r8a779f0_pre_init;
|
||||
goto out;
|
||||
|
||||
fallback:
|
||||
dev_info(dev, "Using ES1.0 init code\n");
|
||||
priv->pre_init = ufs_renesas_r8a779f0_es10_pre_init;
|
||||
|
||||
out:
|
||||
kfree(data);
|
||||
if (!IS_ERR_OR_NULL(cell))
|
||||
nvmem_cell_put(cell);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ufs_renesas_exit(struct ufs_hba *hba)
|
||||
{
|
||||
struct ufs_renesas_priv *priv = ufshcd_get_variant(hba);
|
||||
|
||||
release_firmware(priv->fw);
|
||||
}
|
||||
|
||||
static int ufs_renesas_set_dma_mask(struct ufs_hba *hba)
|
||||
{
|
||||
return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
|
||||
|
|
@ -378,6 +520,7 @@ static int ufs_renesas_set_dma_mask(struct ufs_hba *hba)
|
|||
static const struct ufs_hba_variant_ops ufs_renesas_vops = {
|
||||
.name = "renesas",
|
||||
.init = ufs_renesas_init,
|
||||
.exit = ufs_renesas_exit,
|
||||
.set_dma_mask = ufs_renesas_set_dma_mask,
|
||||
.setup_clocks = ufs_renesas_setup_clocks,
|
||||
.hce_enable_notify = ufs_renesas_hce_enable_notify,
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user