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ARM: dts: ux500: Tag Janice display SPI correct

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The s6e63m0 display used "type 3" SPI communication so
flag the device as using negative clocking and polarity
on the SPI bus.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij 2021-06-11 15:01:59 +02:00
parent 6880fa6c56
commit ffc011b696
1 changed files with 3 additions and 0 deletions
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3
arch/arm/boot/dts/ste-ux500-samsung-janice.dts
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@ -266,6 +266,9 @@ panel@0 {
pinctrl-names = "default";
pinctrl-0 = <&panel_default_mode>;
spi-3wire;
/* TYPE 3: inverse clock polarity and phase */
spi-cpha;
spi-cpol;
port {
panel_in: endpoint {