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media: chips-media: wave5: Add support for background detection

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Implement V4L2_CID_MPEG_VIDEO_BACKGROUND_DETECTION in the Wave5 encoder
driver. When enabled, the hardware detects background regions in a frame
and uses fewer bits or skip mode to encode them, reducing bitrate for
streams with stationary scenes.

Signed-off-by: Jackson Lee <jackson.lee@chipsnmedia.com>
Signed-off-by: Nas Chung <nas.chung@chipsnmedia.com>
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
This commit is contained in:
Jackson Lee 2026-03-24 14:03:58 +09:00 committed by Hans Verkuil
parent 5d801b5963
commit ffa7cb083c
3 changed files with 11 additions and 1 deletions
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4
drivers/media/platform/chips-media/wave5/wave5-hw.c
View File

@ -49,6 +49,7 @@
#define FASTIO_ADDRESS_MASK GENMASK(15, 0)
#define SEQ_PARAM_PROFILE_MASK GENMASK(30, 24)
#define SEQ_BG_PARAM_REG_DATA 0x3800410
static void _wave5_print_reg_err(struct vpu_device *vpu_dev, u32 reg_fail_reason,
const char *func);
@ -1838,7 +1839,8 @@ int wave5_vpu_enc_init_seq(struct vpu_instance *inst)
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_4_7, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_ROT_PARAM, rot_mir_mode);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_BG_PARAM, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_BG_PARAM,
SEQ_BG_PARAM_REG_DATA | p_param->bg_detection);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_LAMBDA_ADDR, 0);
vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CONF_WIN_TOP_BOT,
p_param->conf_win_bot << 16 | p_param->conf_win_top);

7
drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c
View File

@ -759,6 +759,9 @@ static int wave5_vpu_enc_s_ctrl(struct v4l2_ctrl *ctrl)
case V4L2_CID_MPEG_VIDEO_BITRATE:
inst->bit_rate = ctrl->val;
break;
case V4L2_CID_MPEG_VIDEO_BACKGROUND_DETECTION:
inst->enc_param.bg_detection = ctrl->val;
break;
case V4L2_CID_MPEG_VIDEO_GOP_SIZE:
inst->enc_param.avc_idr_period = ctrl->val;
break;
@ -1184,6 +1187,7 @@ static int wave5_set_enc_openparam(struct enc_open_param *open_param,
open_param->wave_param.beta_offset_div2 = input.beta_offset_div2;
open_param->wave_param.decoding_refresh_type = input.decoding_refresh_type;
open_param->wave_param.intra_period = input.intra_period;
open_param->wave_param.bg_detection = input.bg_detection;
if (inst->std == W_HEVC_ENC) {
if (input.intra_period == 0) {
open_param->wave_param.decoding_refresh_type = DEC_REFRESH_TYPE_IDR;
@ -1679,6 +1683,9 @@ static int wave5_vpu_open_enc(struct file *filp)
v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops,
V4L2_CID_MPEG_VIDEO_AU_DELIMITER,
0, 1, 1, 1);
v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops,
V4L2_CID_MPEG_VIDEO_BACKGROUND_DETECTION,
0, 1, 1, 0);
v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops,
V4L2_CID_HFLIP,
0, 1, 1, 0);

1
drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
View File

@ -570,6 +570,7 @@ struct enc_wave_param {
u32 transform8x8_enable: 1; /* enable 8x8 intra prediction and 8x8 transform */
u32 mb_level_rc_enable: 1; /* enable MB-level rate control */
u32 forced_idr_header_enable: 1; /* enable header encoding before IDR frame */
u32 bg_detection: 1; /* enable background detection */
};
struct enc_open_param {