mirror of
https://github.com/torvalds/linux.git
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Merge a99163e9e7 ("Merge tag 'devicetree-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux") into android-mainline
Steps on the way to 5.12-rc1 Signed-off-by: Greg Kroah-Hartman <gregkh@google.com> Change-Id: Iabdeafaf576f0e547a4380a9ecb478e0db7ae4b3
This commit is contained in:
Greg Kroah-Hartman
commit
ff9463f365
1
.gitignore
vendored
1
.gitignore
vendored
|
|
@ -18,6 +18,7 @@
|
|||
*.c.[012]*.*
|
||||
*.dt.yaml
|
||||
*.dtb
|
||||
*.dtbo
|
||||
*.dtb.S
|
||||
*.dwo
|
||||
*.elf
|
||||
|
|
|
|||
82
Documentation/ABI/testing/sysfs-class-power-ltc4162l
Normal file
82
Documentation/ABI/testing/sysfs-class-power-ltc4162l
Normal file
|
|
@ -0,0 +1,82 @@
|
|||
What: /sys/class/power_supply/ltc4162-l/charge_status
|
||||
Date: Januari 2021
|
||||
KernelVersion: 5.11
|
||||
Description:
|
||||
Detailed charge status information as reported by the chip.
|
||||
|
||||
Access: Read
|
||||
|
||||
Valid values:
|
||||
ilim_reg_active
|
||||
thermal_reg_active
|
||||
vin_uvcl_active
|
||||
iin_limit_active
|
||||
constant_current
|
||||
constant_voltage
|
||||
charger_off
|
||||
|
||||
What: /sys/class/power_supply/ltc4162-l/ibat
|
||||
Date: Januari 2021
|
||||
KernelVersion: 5.11
|
||||
Description:
|
||||
Battery input current as measured by the charger. Negative value
|
||||
means that the battery is discharging.
|
||||
|
||||
Access: Read
|
||||
|
||||
Valid values: Signed value in microamps
|
||||
|
||||
What: /sys/class/power_supply/ltc4162-l/vbat
|
||||
Date: Januari 2021
|
||||
KernelVersion: 5.11
|
||||
Description:
|
||||
Battery voltage as measured by the charger.
|
||||
|
||||
Access: Read
|
||||
|
||||
Valid values: In microvolts
|
||||
|
||||
What: /sys/class/power_supply/ltc4162-l/vbat_avg
|
||||
Date: Januari 2021
|
||||
KernelVersion: 5.11
|
||||
Description:
|
||||
Battery voltage, averaged over time, as measured by the charger.
|
||||
|
||||
Access: Read
|
||||
|
||||
Valid values: In microvolts
|
||||
|
||||
What: /sys/class/power_supply/ltc4162-l/force_telemetry
|
||||
Date: Januari 2021
|
||||
KernelVersion: 5.11
|
||||
Description:
|
||||
To save battery current, the measurement system is disabled if
|
||||
the battery is the only source of power. This affects all
|
||||
voltage, current and temperature measurements.
|
||||
Write a "1" to this to keep performing telemetry once every few
|
||||
seconds, even when running on battery (as reported by the online
|
||||
property, which is "1" when external power is available and "0"
|
||||
when the system runs on battery).
|
||||
|
||||
Access: Read, Write
|
||||
|
||||
Valid values: 0 (disabled) or 1 (enabled)
|
||||
|
||||
What: /sys/class/power_supply/ltc4162-l/arm_ship_mode
|
||||
Date: Januari 2021
|
||||
KernelVersion: 5.11
|
||||
Description:
|
||||
The charger will normally drain the battery while inactive,
|
||||
typically drawing about 54 microamps. Write a "1" to this
|
||||
property to arm a special "ship" mode that extends shelf life
|
||||
by reducing the leakage to about 2.8 microamps. The chip will
|
||||
remain in this mode (and no longer respond to I2C commands)
|
||||
until some external power-supply is attached raising the input
|
||||
voltage above 1V. It will then automatically revert to "0".
|
||||
Writing a "0" to the property cancels the "ship" mode request.
|
||||
The ship mode, when armed, activates once the input voltage
|
||||
drops below 1V.
|
||||
|
||||
Access: Read, Write
|
||||
|
||||
Valid values: 0 (disable) or 1 (enable)
|
||||
|
|
@ -10,7 +10,7 @@ DT_SCHEMA_MIN_VERSION = 2020.8.1
|
|||
PHONY += check_dtschema_version
|
||||
check_dtschema_version:
|
||||
@{ echo $(DT_SCHEMA_MIN_VERSION); \
|
||||
$(DT_DOC_CHECKER) --version 2>/dev/null || echo 0; } | sort -VC || \
|
||||
$(DT_DOC_CHECKER) --version 2>/dev/null || echo 0; } | sort -Vc >/dev/null || \
|
||||
{ echo "ERROR: dtschema minimum version is v$(DT_SCHEMA_MIN_VERSION)" >&2; false; }
|
||||
|
||||
quiet_cmd_extract_ex = DTEX $@
|
||||
|
|
|
|||
|
|
@ -91,7 +91,8 @@ SHDWC SAMA5D2-Compatible Shutdown Controller
|
|||
1) shdwc node
|
||||
|
||||
required properties:
|
||||
- compatible: should be "atmel,sama5d2-shdwc" or "microchip,sam9x60-shdwc".
|
||||
- compatible: should be "atmel,sama5d2-shdwc", "microchip,sam9x60-shdwc" or
|
||||
"microchip,sama7g5-shdwc"
|
||||
- reg: should contain registers location and length
|
||||
- clocks: phandle to input clock.
|
||||
- #address-cells: should be one. The cell is the wake-up input index.
|
||||
|
|
@ -103,7 +104,7 @@ optional properties:
|
|||
microseconds. It's usually a board-related property.
|
||||
- atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up.
|
||||
|
||||
optional microchip,sam9x60-shdwc properties:
|
||||
optional microchip,sam9x60-shdwc or microchip,sama7g5-shdwc properties:
|
||||
- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
|
||||
|
||||
The node contains child nodes for each wake-up input that the platform uses.
|
||||
|
|
|
|||
|
|
@ -80,6 +80,11 @@ Required properties:
|
|||
|
||||
- offset: offset address inside the syscon block
|
||||
|
||||
Optional properties:
|
||||
|
||||
- marvell,pwm-offset: offset address of PWM duration control registers inside
|
||||
the syscon block
|
||||
|
||||
Example:
|
||||
ap_syscon: system-controller@6f4000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
|
|
@ -101,6 +106,9 @@ ap_syscon: system-controller@6f4000 {
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&ap_pinctrl 0 0 19>;
|
||||
marvell,pwm-offset = <0x10c0>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&ap_clk 3>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -30,8 +30,8 @@ properties:
|
|||
Interrupts can be used to notify the completion of cache operations.
|
||||
The number of interrupts should match to the number of CPU cores.
|
||||
The specified interrupts correspond to CPU0, CPU1, ... in this order.
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
cache-unified: true
|
||||
|
||||
|
|
|
|||
|
|
@ -61,6 +61,7 @@ properties:
|
|||
maxItems: 8
|
||||
|
||||
calxeda,sgpio-gpio:
|
||||
maxItems: 3
|
||||
description: |
|
||||
phandle-gpio bank, bit offset, and default on or off, which indicates
|
||||
that the driver supports SGPIO indicator lights using the indicated
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@ properties:
|
|||
compatible:
|
||||
enum:
|
||||
- adi,axi-clkgen-2.00.a
|
||||
- adi,zynqmp-axi-clkgen-2.00.a
|
||||
|
||||
clocks:
|
||||
description:
|
||||
|
|
|
|||
|
|
@ -41,6 +41,8 @@ properties:
|
|||
- allwinner,sun50i-h5-ccu
|
||||
- allwinner,sun50i-h6-ccu
|
||||
- allwinner,sun50i-h6-r-ccu
|
||||
- allwinner,sun50i-h616-ccu
|
||||
- allwinner,sun50i-h616-r-ccu
|
||||
- allwinner,suniv-f1c100s-ccu
|
||||
- nextthing,gr8-ccu
|
||||
|
||||
|
|
@ -82,6 +84,7 @@ if:
|
|||
- allwinner,sun50i-a64-r-ccu
|
||||
- allwinner,sun50i-a100-r-ccu
|
||||
- allwinner,sun50i-h6-r-ccu
|
||||
- allwinner,sun50i-h616-r-ccu
|
||||
|
||||
then:
|
||||
properties:
|
||||
|
|
@ -100,6 +103,7 @@ else:
|
|||
enum:
|
||||
- allwinner,sun50i-a100-ccu
|
||||
- allwinner,sun50i-h6-ccu
|
||||
- allwinner,sun50i-h616-ccu
|
||||
|
||||
then:
|
||||
properties:
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-usb-clocks.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-usb-clks.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A80 USB Clock Controller Device Tree Bindings
|
||||
|
|
@ -18,7 +18,7 @@ properties:
|
|||
const: 1
|
||||
|
||||
compatible:
|
||||
const: allwinner,sun9i-a80-usb-clocks
|
||||
const: allwinner,sun9i-a80-usb-clks
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
@ -66,8 +66,8 @@ properties:
|
|||
- arm,syscon-icst525-integratorcp-cm-mem
|
||||
- arm,integrator-cm-auxosc
|
||||
- arm,versatile-cm-auxosc
|
||||
- arm,impd-vco1
|
||||
- arm,impd-vco2
|
||||
- arm,impd1-vco1
|
||||
- arm,impd1-vco2
|
||||
|
||||
clocks:
|
||||
description: Parent clock for the ICST VCO
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@ properties:
|
|||
const: canaan,k210-clk
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
description:
|
||||
Phandle of the SoC 26MHz fixed-rate oscillator clock.
|
||||
|
||||
|
|
|
|||
|
|
@ -1,55 +0,0 @@
|
|||
* Clock and reset bindings for CSR atlas7
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "sirf,atlas7-car"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
- #reset-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell.
|
||||
The ID list atlas7_clks defined in drivers/clk/sirf/clk-atlas7.c
|
||||
|
||||
The reset consumer should specify the desired reset by having the reset
|
||||
ID in its "reset" phandle cell.
|
||||
The ID list atlas7_reset_unit defined in drivers/clk/sirf/clk-atlas7.c
|
||||
|
||||
Examples: Clock and reset controller node:
|
||||
|
||||
car: clock-controller@18620000 {
|
||||
compatible = "sirf,atlas7-car";
|
||||
reg = <0x18620000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Examples: Consumers using clock or reset:
|
||||
|
||||
timer@10dc0000 {
|
||||
compatible = "sirf,macro-tick";
|
||||
reg = <0x10dc0000 0x1000>;
|
||||
clocks = <&car 54>;
|
||||
interrupts = <0 0 0>,
|
||||
<0 1 0>,
|
||||
<0 2 0>,
|
||||
<0 49 0>,
|
||||
<0 50 0>,
|
||||
<0 51 0>;
|
||||
};
|
||||
|
||||
uart1: uart@18020000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,macro-uart";
|
||||
reg = <0x18020000 0x1000>;
|
||||
clocks = <&clks 95>;
|
||||
interrupts = <0 18 0>;
|
||||
fifosize = <32>;
|
||||
};
|
||||
|
||||
vpp@13110000 {
|
||||
compatible = "sirf,prima2-vpp";
|
||||
reg = <0x13110000 0x10000>;
|
||||
interrupts = <0 31 0>;
|
||||
clocks = <&car 85>;
|
||||
resets = <&car 29>;
|
||||
};
|
||||
|
|
@ -59,6 +59,12 @@ properties:
|
|||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
idt,xtal-load-femtofarads:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 9000
|
||||
maximum: 22760
|
||||
description: Optional load capacitor for XTAL1 and XTAL2
|
||||
|
||||
patternProperties:
|
||||
"^OUT[1-4]$":
|
||||
type: object
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Clock bindings for Freescale i.MX27
|
||||
|
||||
maintainers:
|
||||
- Fabio Estevam <fabio.estevam@nxp.com>
|
||||
- Fabio Estevam <festevam@gmail.com>
|
||||
|
||||
description: |
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Clock bindings for Freescale i.MX31
|
||||
|
||||
maintainers:
|
||||
- Fabio Estevam <fabio.estevam@nxp.com>
|
||||
- Fabio Estevam <festevam@gmail.com>
|
||||
|
||||
description: |
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Clock bindings for Freescale i.MX5
|
||||
|
||||
maintainers:
|
||||
- Fabio Estevam <fabio.estevam@nxp.com>
|
||||
- Fabio Estevam <festevam@gmail.com>
|
||||
|
||||
description: |
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
|
|
|
|||
46
Documentation/devicetree/bindings/clock/intel,easic-n5x.yaml
Normal file
46
Documentation/devicetree/bindings/clock/intel,easic-n5x.yaml
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/intel,easic-n5x.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Intel SoCFPGA eASIC N5X platform clock controller binding
|
||||
|
||||
maintainers:
|
||||
- Dinh Nguyen <dinguyen@kernel.org>
|
||||
|
||||
description:
|
||||
The Intel eASIC N5X Clock controller is an integrated clock controller, which
|
||||
generates and supplies to all modules.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: intel,easic-n5x-clkmgr
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Clock controller node:
|
||||
- |
|
||||
clkmgr: clock-controller@ffd10000 {
|
||||
compatible = "intel,easic-n5x-clkmgr";
|
||||
reg = <0xffd10000 0x1000>;
|
||||
clocks = <&osc1>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/mstar,msc313-mpll.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MStar/Sigmastar MSC313 MPLL
|
||||
|
||||
maintainers:
|
||||
- Daniel Palmer <daniel@thingy.jp>
|
||||
|
||||
description: |
|
||||
The MStar/SigmaStar MSC313 and later ARMv7 chips have an MPLL block that
|
||||
takes the external xtal input and multiplies it to create a high
|
||||
frequency clock and divides that down into a number of clocks that
|
||||
peripherals use.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: mstar,msc313-mpll
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
mpll@206000 {
|
||||
compatible = "mstar,msc313-mpll";
|
||||
reg = <0x206000 0x200>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&xtal>;
|
||||
};
|
||||
|
|
@ -1,73 +0,0 @@
|
|||
* Clock bindings for CSR SiRFprimaII
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "sirf,prima2-clkc"
|
||||
- reg: Address and length of the register set
|
||||
- interrupts: Should contain clock controller interrupt
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. The following is a full list of prima2
|
||||
clocks and IDs.
|
||||
|
||||
Clock ID
|
||||
---------------------------
|
||||
rtc 0
|
||||
osc 1
|
||||
pll1 2
|
||||
pll2 3
|
||||
pll3 4
|
||||
mem 5
|
||||
sys 6
|
||||
security 7
|
||||
dsp 8
|
||||
gps 9
|
||||
mf 10
|
||||
io 11
|
||||
cpu 12
|
||||
uart0 13
|
||||
uart1 14
|
||||
uart2 15
|
||||
tsc 16
|
||||
i2c0 17
|
||||
i2c1 18
|
||||
spi0 19
|
||||
spi1 20
|
||||
pwmc 21
|
||||
efuse 22
|
||||
pulse 23
|
||||
dmac0 24
|
||||
dmac1 25
|
||||
nand 26
|
||||
audio 27
|
||||
usp0 28
|
||||
usp1 29
|
||||
usp2 30
|
||||
vip 31
|
||||
gfx 32
|
||||
mm 33
|
||||
lcd 34
|
||||
vpp 35
|
||||
mmc01 36
|
||||
mmc23 37
|
||||
mmc45 38
|
||||
usbpll 39
|
||||
usb0 40
|
||||
usb1 41
|
||||
|
||||
Examples:
|
||||
|
||||
clks: clock-controller@88000000 {
|
||||
compatible = "sirf,prima2-clkc";
|
||||
reg = <0x88000000 0x1000>;
|
||||
interrupts = <3>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
i2c0: i2c@b00e0000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,prima2-i2c";
|
||||
reg = <0xb00e0000 0x10000>;
|
||||
interrupts = <24>;
|
||||
clocks = <&clks 17>;
|
||||
};
|
||||
51
Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
Normal file
51
Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,a7pll.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm A7 PLL Binding
|
||||
|
||||
maintainers:
|
||||
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
description:
|
||||
The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high
|
||||
frequency clock to the CPU.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sdx55-a7pll
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: board XO clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
a7pll: clock@17808000 {
|
||||
compatible = "qcom,sdx55-a7pll";
|
||||
reg = <0x17808000 0x1000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "bi_tcxo";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
92
Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
Normal file
92
Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
Normal file
|
|
@ -0,0 +1,92 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sc7280.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SC7280
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SC7280.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sc7280.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-sc7280
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board active XO source
|
||||
- description: Sleep clock source
|
||||
- description: PCIE-0 pipe clock source
|
||||
- description: PCIE-1 pipe clock source
|
||||
- description: USF phy rx symbol 0 clock source
|
||||
- description: USF phy rx symbol 1 clock source
|
||||
- description: USF phy tx symbol 0 clock source
|
||||
- description: USB30 phy wrapper pipe clock source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: bi_tcxo_ao
|
||||
- const: sleep_clk
|
||||
- const: pcie_0_pipe_clk
|
||||
- const: pcie_1_pipe_clk
|
||||
- const: ufs_phy_rx_symbol_0_clk
|
||||
- const: ufs_phy_rx_symbol_1_clk
|
||||
- const: ufs_phy_tx_symbol_0_clk
|
||||
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sc7280";
|
||||
reg = <0x00100000 0x1f0000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>,
|
||||
<&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>,
|
||||
<&ufs_phy_rx_symbol_0_clk>, <&ufs_phy_rx_symbol_1_clk>,
|
||||
<&ufs_phy_tx_symbol_0_clk>,
|
||||
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
|
||||
|
||||
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk",
|
||||
"pcie_1_pipe_clk", "ufs_phy_rx_symbol_0_clk",
|
||||
"ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk",
|
||||
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sc8180x.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SC8180x
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SC8180x.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sc8180x.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-sc8180x
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board active XO source
|
||||
- description: Sleep clock source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: bi_tcxo_ao
|
||||
- const: sleep_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sc8180x";
|
||||
reg = <0x00100000 0x1f0000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>;
|
||||
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
96
Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
Normal file
96
Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
Normal file
|
|
@ -0,0 +1,96 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8350.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SM8350
|
||||
|
||||
maintainers:
|
||||
- Vinod Koul <vkoul@kernel.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SM8350.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sm8350.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-sm8350
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Sleep clock source
|
||||
- description: PLL test clock source (Optional clock)
|
||||
- description: PCIE 0 Pipe clock source (Optional clock)
|
||||
- description: PCIE 1 Pipe clock source (Optional clock)
|
||||
- description: UFS card Rx symbol 0 clock source (Optional clock)
|
||||
- description: UFS card Rx symbol 1 clock source (Optional clock)
|
||||
- description: UFS card Tx symbol 0 clock source (Optional clock)
|
||||
- description: UFS phy Rx symbol 0 clock source (Optional clock)
|
||||
- description: UFS phy Rx symbol 1 clock source (Optional clock)
|
||||
- description: UFS phy Tx symbol 0 clock source (Optional clock)
|
||||
- description: USB3 phy wrapper pipe clock source (Optional clock)
|
||||
- description: USB3 phy sec pipe clock source (Optional clock)
|
||||
minItems: 2
|
||||
maxItems: 13
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: sleep_clk
|
||||
- const: core_bi_pll_test_se # Optional clock
|
||||
- const: pcie_0_pipe_clk # Optional clock
|
||||
- const: pcie_1_pipe_clk # Optional clock
|
||||
- const: ufs_card_rx_symbol_0_clk # Optional clock
|
||||
- const: ufs_card_rx_symbol_1_clk # Optional clock
|
||||
- const: ufs_card_tx_symbol_0_clk # Optional clock
|
||||
- const: ufs_phy_rx_symbol_0_clk # Optional clock
|
||||
- const: ufs_phy_rx_symbol_1_clk # Optional clock
|
||||
- const: ufs_phy_tx_symbol_0_clk # Optional clock
|
||||
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
|
||||
- const: usb3_uni_phy_sec_gcc_usb30_pipe_clk # Optional clock
|
||||
minItems: 2
|
||||
maxItems: 13
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sm8350";
|
||||
reg = <0x00100000 0x1f0000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&sleep_clk>;
|
||||
clock-names = "bi_tcxo", "sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gpucc-sdm660.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Graphics Clock & Reset Controller Binding for SDM630 and SDM660
|
||||
|
||||
maintainers:
|
||||
- AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
|
||||
|
||||
description: |
|
||||
Qualcomm graphics clock control module which supports the clocks, resets and
|
||||
power domains on SDM630 and SDM660.
|
||||
|
||||
See also dt-bindings/clock/qcom,gpucc-sdm660.h.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,gpucc-sdm630
|
||||
- qcom,gpucc-sdm660
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: GPLL0 main gpu branch
|
||||
- description: GPLL0 divider gpu branch
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: gcc_gpu_gpll0_clk
|
||||
- const: gcc_gpu_gpll0_div_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sdm660.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
|
||||
clock-controller@5065000 {
|
||||
compatible = "qcom,gpucc-sdm660";
|
||||
reg = <0x05065000 0x9038>;
|
||||
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_CLK>,
|
||||
<&gcc GCC_GPU_GPLL0_DIV_CLK>;
|
||||
clock-names = "xo", "gcc_gpu_gpll0_clk",
|
||||
"gcc_gpu_gpll0_div_clk";
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
@ -24,6 +24,8 @@ properties:
|
|||
- qcom,mmcc-msm8974
|
||||
- qcom,mmcc-msm8996
|
||||
- qcom,mmcc-msm8998
|
||||
- qcom,mmcc-sdm630
|
||||
- qcom,mmcc-sdm660
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
|
|
|||
|
|
@ -18,6 +18,8 @@ properties:
|
|||
compatible:
|
||||
enum:
|
||||
- qcom,sc7180-rpmh-clk
|
||||
- qcom,sc7280-rpmh-clk
|
||||
- qcom,sc8180x-rpmh-clk
|
||||
- qcom,sdm845-rpmh-clk
|
||||
- qcom,sdx55-rpmh-clk
|
||||
- qcom,sm8150-rpmh-clk
|
||||
|
|
|
|||
|
|
@ -35,6 +35,9 @@ properties:
|
|||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- renesas,r8a774a1-rcar-usb2-clock-sel # RZ/G2M
|
||||
- renesas,r8a774b1-rcar-usb2-clock-sel # RZ/G2N
|
||||
- renesas,r8a774e1-rcar-usb2-clock-sel # RZ/G2H
|
||||
- renesas,r8a7795-rcar-usb2-clock-sel # R-Car H3
|
||||
- renesas,r8a7796-rcar-usb2-clock-sel # R-Car M3-W
|
||||
- renesas,r8a77961-rcar-usb2-clock-sel # R-Car M3-W+
|
||||
|
|
|
|||
|
|
@ -28,6 +28,8 @@ Optional properties:
|
|||
- clock-frequency: Output frequency to generate. This defines the output
|
||||
frequency set during boot. It can be reprogrammed during
|
||||
runtime through the common clock framework.
|
||||
- silabs,skip-recall: Do not perform NVM->RAM recall operation. It will rely
|
||||
on hardware loading of RAM from NVM at power on.
|
||||
|
||||
Example:
|
||||
si570: clock-generator@5d {
|
||||
|
|
|
|||
|
|
@ -1,80 +0,0 @@
|
|||
Clock bindings for ST-Ericsson U300 System Controller Clocks
|
||||
|
||||
Bindings for the gated system controller clocks:
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "stericsson,u300-syscon-clk"
|
||||
- #clock-cells: must be <0>
|
||||
- clock-type: specifies the type of clock:
|
||||
0 = slow clock
|
||||
1 = fast clock
|
||||
2 = rest/remaining clock
|
||||
- clock-id: specifies the clock in the type range
|
||||
|
||||
Optional properties:
|
||||
- clocks: parent clock(s)
|
||||
|
||||
The available clocks per type are as follows:
|
||||
|
||||
Type: ID: Clock:
|
||||
-------------------
|
||||
0 0 Slow peripheral bridge clock
|
||||
0 1 UART0 clock
|
||||
0 4 GPIO clock
|
||||
0 6 RTC clock
|
||||
0 7 Application timer clock
|
||||
0 8 Access timer clock
|
||||
|
||||
1 0 Fast peripheral bridge clock
|
||||
1 1 I2C bus 0 clock
|
||||
1 2 I2C bus 1 clock
|
||||
1 5 MMC interface peripheral (silicon) clock
|
||||
1 6 SPI clock
|
||||
|
||||
2 3 CPU clock
|
||||
2 4 DMA controller clock
|
||||
2 5 External Memory Interface (EMIF) clock
|
||||
2 6 NAND flask interface clock
|
||||
2 8 XGAM graphics engine clock
|
||||
2 9 Shared External Memory Interface (SEMI) clock
|
||||
2 10 AHB Subsystem Bridge clock
|
||||
2 12 Interrupt controller clock
|
||||
|
||||
Example:
|
||||
|
||||
gpio_clk: gpio_clk@13M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "stericsson,u300-syscon-clk";
|
||||
clock-type = <0>; /* Slow */
|
||||
clock-id = <4>;
|
||||
clocks = <&slow_clk>;
|
||||
};
|
||||
|
||||
gpio: gpio@c0016000 {
|
||||
compatible = "stericsson,gpio-coh901";
|
||||
(...)
|
||||
clocks = <&gpio_clk>;
|
||||
};
|
||||
|
||||
|
||||
Bindings for the MMC/SD card clock:
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "stericsson,u300-syscon-mclk"
|
||||
- #clock-cells: must be <0>
|
||||
|
||||
Optional properties:
|
||||
- clocks: parent clock(s)
|
||||
|
||||
mmc_mclk: mmc_mclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "stericsson,u300-syscon-mclk";
|
||||
clocks = <&mmc_pclk>;
|
||||
};
|
||||
|
||||
mmcsd: mmcsd@c0001000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
clocks = <&mmc_pclk>, <&mmc_mclk>;
|
||||
clock-names = "apb_pclk", "mclk";
|
||||
(...)
|
||||
};
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
* Sigma Designs Tango4 Clock Generator
|
||||
|
||||
The Tango4 clock generator outputs cpu_clk and sys_clk (the latter is used
|
||||
for RAM and various peripheral devices). The clock binding described here
|
||||
is applicable to all Tango4 SoCs.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "sigma,tango4-clkgen".
|
||||
- reg: physical base address of the device and length of memory mapped region.
|
||||
- clocks: phandle of the input clock (crystal oscillator).
|
||||
- clock-output-names: should be "cpuclk" and "sysclk".
|
||||
- #clock-cells: should be set to 1.
|
||||
|
||||
Example:
|
||||
|
||||
clkgen: clkgen@10000 {
|
||||
compatible = "sigma,tango4-clkgen";
|
||||
reg = <0x10000 0x40>;
|
||||
clocks = <&xtal>;
|
||||
clock-output-names = "cpuclk", "sysclk";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -1,34 +0,0 @@
|
|||
Device Tree Clock bindings for ZTE zx296702
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be one of the following:
|
||||
"zte,zx296702-topcrm-clk":
|
||||
zx296702 top clock selection, divider and gating
|
||||
|
||||
"zte,zx296702-lsp0crpm-clk" and
|
||||
"zte,zx296702-lsp1crpm-clk":
|
||||
zx296702 device level clock selection and gating
|
||||
|
||||
- reg: Address and length of the register set
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296702-clock.h
|
||||
for the full list of zx296702 clock IDs.
|
||||
|
||||
|
||||
topclk: topcrm@09800000 {
|
||||
compatible = "zte,zx296702-topcrm-clk";
|
||||
reg = <0x09800000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
uart0: serial@09405000 {
|
||||
compatible = "zte,zx296702-uart";
|
||||
reg = <0x09405000 0x1000>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&lsp1clk ZX296702_UART0_PCLK>;
|
||||
};
|
||||
|
|
@ -1,37 +0,0 @@
|
|||
Device Tree Clock bindings for ZTE zx296718
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be one of the following:
|
||||
"zte,zx296718-topcrm":
|
||||
zx296718 top clock selection, divider and gating
|
||||
|
||||
"zte,zx296718-lsp0crm" and
|
||||
"zte,zx296718-lsp1crm":
|
||||
zx296718 device level clock selection and gating
|
||||
|
||||
"zte,zx296718-audiocrm":
|
||||
zx296718 audio clock selection, divider and gating
|
||||
|
||||
- reg: Address and length of the register set
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296718-clock.h
|
||||
for the full list of zx296718 clock IDs.
|
||||
|
||||
|
||||
topclk: topcrm@1461000 {
|
||||
compatible = "zte,zx296718-topcrm-clk";
|
||||
reg = <0x01461000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
usbphy0:usb-phy0 {
|
||||
compatible = "zte,zx296718-usb-phy";
|
||||
#phy-cells = <0>;
|
||||
clocks = <&topclk USB20_PHY_CLK>;
|
||||
clock-names = "phyclk";
|
||||
};
|
||||
|
|
@ -155,22 +155,23 @@ properties:
|
|||
power dual role.
|
||||
|
||||
ports:
|
||||
description: OF graph bindings (specified in bindings/graph.txt) that model
|
||||
any data bus to the connector unless the bus is between parent node and
|
||||
the connector. Since a single connector can have multiple data buses every
|
||||
bus has an assigned OF graph port number as described below.
|
||||
type: object
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description: OF graph bindings modeling any data bus to the connector
|
||||
unless the bus is between parent node and the connector. Since a single
|
||||
connector can have multiple data buses every bus has an assigned OF graph
|
||||
port number as described below.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
type: object
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: High Speed (HS), present in all connectors.
|
||||
|
||||
port@1:
|
||||
type: object
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Super Speed (SS), present in SS capable connectors.
|
||||
|
||||
port@2:
|
||||
type: object
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Sideband Use (SBU), present in USB-C. This describes the
|
||||
alternate mode connection of which SBU is a part.
|
||||
|
||||
|
|
|
|||
|
|
@ -46,8 +46,7 @@ properties:
|
|||
if:
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
const: allwinner,sun50i-h6-crypto
|
||||
const: allwinner,sun50i-h6-crypto
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
|
|
|
|||
|
|
@ -66,7 +66,7 @@ examples:
|
|||
#include <dt-bindings/soc/ti,sci_pm_domain.h>
|
||||
|
||||
main_crypto: crypto@4e00000 {
|
||||
compatible = "ti,j721-sa2ul";
|
||||
compatible = "ti,j721e-sa2ul";
|
||||
reg = <0x4e00000 0x1200>;
|
||||
power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
|
||||
dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
|
||||
|
|
|
|||
|
|
@ -78,6 +78,7 @@ properties:
|
|||
Phandle of the I2C controller used for DDC EDID probing
|
||||
|
||||
hpd-gpios:
|
||||
maxItems: 1
|
||||
description: >
|
||||
The GPIO pin for the HDMI hotplug detect (if it doesn't appear
|
||||
as an interrupt/status bit in the HDMI controller itself)
|
||||
|
|
|
|||
|
|
@ -37,6 +37,7 @@ properties:
|
|||
Phandle of the I2C controller used for DDC EDID probing
|
||||
|
||||
hpd-gpios:
|
||||
maxItems: 1
|
||||
description: >
|
||||
The GPIO pin for the HDMI hotplug detect (if it doesn't appear
|
||||
as an interrupt/status bit in the HDMI controller itself)
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@ if:
|
|||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: brcm,bcm2711-hvs"
|
||||
const: brcm,bcm2711-hvs
|
||||
|
||||
then:
|
||||
required:
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@ properties:
|
|||
power supply for LCM (1.8V)
|
||||
|
||||
dcdc-en-gpios:
|
||||
maxItems: 1
|
||||
description: |
|
||||
phandle of the gpio for power ic line
|
||||
Power IC supply enable, High active
|
||||
|
|
|
|||
|
|
@ -38,7 +38,8 @@ properties:
|
|||
|
||||
reset-gpios: true
|
||||
|
||||
'mantix,tp-rstn-gpios':
|
||||
mantix,tp-rstn-gpios:
|
||||
maxItems: 1
|
||||
description: second reset line that triggers DSI config load
|
||||
|
||||
backlight: true
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@ properties:
|
|||
panel. The novatek,nt36672a compatible shall always be provided as a fallback.
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
description: phandle of gpio for reset line - This should be 8mA, gpio
|
||||
can be configured using mux, pinctrl, pinctrl-names (active high)
|
||||
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@ properties:
|
|||
- fsl,imx8mp-dsp
|
||||
|
||||
reg:
|
||||
description: Should contain register location and length
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
|
|
|||
|
|
@ -39,8 +39,7 @@ properties:
|
|||
- const: atmel,at25
|
||||
|
||||
reg:
|
||||
description:
|
||||
Chip select number.
|
||||
maxItems: 1
|
||||
|
||||
spi-max-frequency: true
|
||||
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@ properties:
|
|||
const: nxp,ptn5150
|
||||
|
||||
int-gpios:
|
||||
maxItems: 1
|
||||
deprecated: true
|
||||
description:
|
||||
GPIO pin (input) connected to the PTN5150's INTB pin.
|
||||
|
|
@ -31,6 +32,7 @@ properties:
|
|||
maxItems: 1
|
||||
|
||||
vbus-gpios:
|
||||
maxItems: 1
|
||||
description:
|
||||
GPIO pin (output) used to control VBUS. If skipped, no such control
|
||||
takes place.
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ Required Properties:
|
|||
"ti,k2g-gpio", "ti,keystone-gpio": for 66AK2G
|
||||
"ti,am654-gpio", "ti,keystone-gpio": for TI K3 AM654
|
||||
"ti,j721e-gpio", "ti,keystone-gpio": for J721E SoCs
|
||||
"ti,am64-gpio", "ti,keystone-gpio": for AM64 SoCs
|
||||
|
||||
- reg: Physical base address of the controller and the size of memory mapped
|
||||
registers.
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@ properties:
|
|||
- maxim,max7327
|
||||
- nxp,pca6416
|
||||
- nxp,pca9505
|
||||
- nxp,pca9506
|
||||
- nxp,pca9534
|
||||
- nxp,pca9535
|
||||
- nxp,pca9536
|
||||
|
|
@ -70,7 +71,7 @@ properties:
|
|||
|
||||
gpio-line-names:
|
||||
minItems: 1
|
||||
maxItems: 32
|
||||
maxItems: 40
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
|
@ -81,6 +82,7 @@ properties:
|
|||
const: 2
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
description:
|
||||
GPIO specification for the RESET input. This is an active low signal to
|
||||
the PCA953x. Not valid for Maxim MAX732x devices.
|
||||
|
|
|
|||
|
|
@ -46,7 +46,7 @@ examples:
|
|||
#include <dt-bindings/gpio/msc313-gpio.h>
|
||||
|
||||
gpio: gpio@207800 {
|
||||
compatible = "mstar,msc313e-gpio";
|
||||
compatible = "mstar,msc313-gpio";
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x207800 0x200>;
|
||||
gpio-controller;
|
||||
|
|
|
|||
|
|
@ -48,6 +48,9 @@ properties:
|
|||
- renesas,gpio-r8a77995 # R-Car D3
|
||||
- const: renesas,rcar-gen3-gpio # R-Car Gen3 or RZ/G2
|
||||
|
||||
- items:
|
||||
- const: renesas,gpio-r8a779a0 # R-Car V3U
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,70 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/gpio/toshiba,gpio-visconti.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Toshiba Visconti ARM SoCs GPIO controller
|
||||
|
||||
maintainers:
|
||||
- Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: toshiba,gpio-tmpv7708
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
gpio-ranges: true
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 2
|
||||
|
||||
interrupts:
|
||||
description:
|
||||
interrupt mapping one per GPIO.
|
||||
minItems: 16
|
||||
maxItems: 16
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#gpio-cells"
|
||||
- gpio-ranges
|
||||
- gpio-controller
|
||||
- interrupt-controller
|
||||
- "#interrupt-cells"
|
||||
- interrupt-parent
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
gpio: gpio@28020000 {
|
||||
compatible = "toshiba,gpio-tmpv7708";
|
||||
reg = <0 0x28020000 0 0x1000>;
|
||||
#gpio-cells = <0x2>;
|
||||
gpio-ranges = <&pmux 0 0 32>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
ZTE ZX296702 GPIO controller
|
||||
|
||||
Required properties:
|
||||
- compatible : "zte,zx296702-gpio"
|
||||
- #gpio-cells : Should be two. The first cell is the pin number and the
|
||||
second cell is used to specify optional parameters:
|
||||
- bit 0 specifies polarity (0 for normal, 1 for inverted)
|
||||
- gpio-controller : Marks the device node as a GPIO controller.
|
||||
- interrupts : Interrupt mapping for GPIO IRQ.
|
||||
- gpio-ranges : Interaction with the PINCTRL subsystem.
|
||||
|
||||
gpio1: gpio@b008040 {
|
||||
compatible = "zte,zx296702-gpio";
|
||||
reg = <0xb008040 0x40>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = < &pmx0 0 54 2 &pmx0 2 59 14>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clock-names = "gpio_pclk";
|
||||
clocks = <&lsp0clk ZX296702_GPIO_CLK>;
|
||||
};
|
||||
|
|
@ -1,33 +0,0 @@
|
|||
Broadcom V3D GPU
|
||||
|
||||
Only the Broadcom V3D 3.x and newer GPUs are covered by this binding.
|
||||
For V3D 2.x, see brcm,bcm-vc4.txt.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "brcm,7268-v3d" or "brcm,7278-v3d"
|
||||
- reg: Physical base addresses and lengths of the register areas
|
||||
- reg-names: Names for the register areas. The "hub" and "core0"
|
||||
register areas are always required. The "gca" register area
|
||||
is required if the GCA cache controller is present. The
|
||||
"bridge" register area is required if an external reset
|
||||
controller is not present.
|
||||
- interrupts: The interrupt numbers. The first interrupt is for the hub,
|
||||
while the following interrupts are separate interrupt lines
|
||||
for the cores (if they don't share the hub's interrupt).
|
||||
See bindings/interrupt-controller/interrupts.txt
|
||||
|
||||
Optional properties:
|
||||
- clocks: The core clock the unit runs on
|
||||
- resets: The reset line for v3d, if not using a mapping of the bridge
|
||||
See bindings/reset/reset.txt
|
||||
|
||||
v3d {
|
||||
compatible = "brcm,7268-v3d";
|
||||
reg = <0xf1204000 0x100>,
|
||||
<0xf1200000 0x4000>,
|
||||
<0xf1208000 0x4000>,
|
||||
<0xf1204100 0x100>;
|
||||
reg-names = "bridge", "hub", "core0", "gca";
|
||||
interrupts = <0 78 4>,
|
||||
<0 77 4>;
|
||||
};
|
||||
75
Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml
Normal file
75
Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml
Normal file
|
|
@ -0,0 +1,75 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/gpu/brcm,bcm-v3d.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom V3D GPU Bindings
|
||||
|
||||
maintainers:
|
||||
- Eric Anholt <eric@anholt.net>
|
||||
- Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: '^gpu@[a-f0-9]+$'
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- brcm,7268-v3d
|
||||
- brcm,7278-v3d
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: hub register (required)
|
||||
- description: core0 register (required)
|
||||
- description: GCA cache controller register (if GCA controller present)
|
||||
- description: bridge register (if no external reset controller)
|
||||
minItems: 2
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: hub
|
||||
- const: core0
|
||||
- enum: [ bridge, gca ]
|
||||
- enum: [ bridge, gca ]
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: hub interrupt (required)
|
||||
- description: core interrupts (if it doesn't share the hub's interrupt)
|
||||
minItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
gpu@f1200000 {
|
||||
compatible = "brcm,7268-v3d";
|
||||
reg = <0xf1200000 0x4000>,
|
||||
<0xf1208000 0x4000>,
|
||||
<0xf1204000 0x100>,
|
||||
<0xf1204100 0x100>;
|
||||
reg-names = "hub", "core0", "bridge", "gca";
|
||||
interrupts = <0 78 4>,
|
||||
<0 77 4>;
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -1,128 +1 @@
|
|||
Common bindings for device graphs
|
||||
|
||||
General concept
|
||||
---------------
|
||||
|
||||
The hierarchical organisation of the device tree is well suited to describe
|
||||
control flow to devices, but there can be more complex connections between
|
||||
devices that work together to form a logical compound device, following an
|
||||
arbitrarily complex graph.
|
||||
There already is a simple directed graph between devices tree nodes using
|
||||
phandle properties pointing to other nodes to describe connections that
|
||||
can not be inferred from device tree parent-child relationships. The device
|
||||
tree graph bindings described herein abstract more complex devices that can
|
||||
have multiple specifiable ports, each of which can be linked to one or more
|
||||
ports of other devices.
|
||||
|
||||
These common bindings do not contain any information about the direction or
|
||||
type of the connections, they just map their existence. Specific properties
|
||||
may be described by specialized bindings depending on the type of connection.
|
||||
|
||||
To see how this binding applies to video pipelines, for example, see
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt.
|
||||
Here the ports describe data interfaces, and the links between them are
|
||||
the connecting data buses. A single port with multiple connections can
|
||||
correspond to multiple devices being connected to the same physical bus.
|
||||
|
||||
Organisation of ports and endpoints
|
||||
-----------------------------------
|
||||
|
||||
Ports are described by child 'port' nodes contained in the device node.
|
||||
Each port node contains an 'endpoint' subnode for each remote device port
|
||||
connected to this port. If a single port is connected to more than one
|
||||
remote device, an 'endpoint' child node must be provided for each link.
|
||||
If more than one port is present in a device node or there is more than one
|
||||
endpoint at a port, or a port node needs to be associated with a selected
|
||||
hardware interface, a common scheme using '#address-cells', '#size-cells'
|
||||
and 'reg' properties is used to number the nodes.
|
||||
|
||||
device {
|
||||
...
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
endpoint@0 {
|
||||
reg = <0>;
|
||||
...
|
||||
};
|
||||
endpoint@1 {
|
||||
reg = <1>;
|
||||
...
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
endpoint { ... };
|
||||
};
|
||||
};
|
||||
|
||||
All 'port' nodes can be grouped under an optional 'ports' node, which
|
||||
allows to specify #address-cells, #size-cells properties for the 'port'
|
||||
nodes independently from any other child device nodes a device might
|
||||
have.
|
||||
|
||||
device {
|
||||
...
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
...
|
||||
endpoint@0 { ... };
|
||||
endpoint@1 { ... };
|
||||
};
|
||||
|
||||
port@1 { ... };
|
||||
};
|
||||
};
|
||||
|
||||
Links between endpoints
|
||||
-----------------------
|
||||
|
||||
Each endpoint should contain a 'remote-endpoint' phandle property that points
|
||||
to the corresponding endpoint in the port of the remote device. In turn, the
|
||||
remote endpoint should contain a 'remote-endpoint' property. If it has one, it
|
||||
must not point to anything other than the local endpoint. Two endpoints with
|
||||
their 'remote-endpoint' phandles pointing at each other form a link between the
|
||||
containing ports.
|
||||
|
||||
device-1 {
|
||||
port {
|
||||
device_1_output: endpoint {
|
||||
remote-endpoint = <&device_2_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
device-2 {
|
||||
port {
|
||||
device_2_input: endpoint {
|
||||
remote-endpoint = <&device_1_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Required properties
|
||||
-------------------
|
||||
|
||||
If there is more than one 'port' or more than one 'endpoint' node or 'reg'
|
||||
property present in the port and/or endpoint nodes then the following
|
||||
properties are required in a relevant parent node:
|
||||
|
||||
- #address-cells : number of cells required to define port/endpoint
|
||||
identifier, should be 1.
|
||||
- #size-cells : should be zero.
|
||||
|
||||
Optional endpoint properties
|
||||
----------------------------
|
||||
|
||||
- remote-endpoint: phandle to an 'endpoint' subnode of a remote device node.
|
||||
|
||||
This file has moved to graph.yaml in dt-schema repo
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ maintainers:
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
const: nuvoton,npcm7xx-i2c
|
||||
const: nuvoton,npcm750-i2c
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -1,140 +0,0 @@
|
|||
Generic device tree bindings for I3C busses
|
||||
===========================================
|
||||
|
||||
This document describes generic bindings that should be used to describe I3C
|
||||
busses in a device tree.
|
||||
|
||||
Required properties
|
||||
-------------------
|
||||
|
||||
- #address-cells - should be <3>. Read more about addresses below.
|
||||
- #size-cells - should be <0>.
|
||||
- compatible - name of the I3C master controller driving the I3C bus
|
||||
|
||||
For other required properties e.g. to describe register sets,
|
||||
clocks, etc. check the binding documentation of the specific driver.
|
||||
The node describing an I3C bus should be named i3c-master.
|
||||
|
||||
Optional properties
|
||||
-------------------
|
||||
|
||||
These properties may not be supported by all I3C master drivers. Each I3C
|
||||
master bindings should specify which of them are supported.
|
||||
|
||||
- i3c-scl-hz: frequency of the SCL signal used for I3C transfers.
|
||||
When undefined the core sets it to 12.5MHz.
|
||||
|
||||
- i2c-scl-hz: frequency of the SCL signal used for I2C transfers.
|
||||
When undefined, the core looks at LVR (Legacy Virtual Register)
|
||||
values of I2C devices described in the device tree to determine
|
||||
the maximum I2C frequency.
|
||||
|
||||
I2C devices
|
||||
===========
|
||||
|
||||
Each I2C device connected to the bus should be described in a subnode. All
|
||||
properties described in Documentation/devicetree/bindings/i2c/i2c.txt are
|
||||
valid here, but several new properties have been added.
|
||||
|
||||
New constraint on existing properties:
|
||||
--------------------------------------
|
||||
- reg: contains 3 cells
|
||||
+ first cell : still encoding the I2C address. 10 bit addressing is not
|
||||
supported. Devices with 10 bit address can't be properly passed through
|
||||
DEFSLVS command.
|
||||
|
||||
+ second cell: shall be 0
|
||||
|
||||
+ third cell: shall encode the I3C LVR (Legacy Virtual Register)
|
||||
bit[31:8]: unused/ignored
|
||||
bit[7:5]: I2C device index. Possible values
|
||||
* 0: I2C device has a 50 ns spike filter
|
||||
* 1: I2C device does not have a 50 ns spike filter but supports high
|
||||
frequency on SCL
|
||||
* 2: I2C device does not have a 50 ns spike filter and is not tolerant
|
||||
to high frequencies
|
||||
* 3-7: reserved
|
||||
|
||||
bit[4]: tell whether the device operates in FM (Fast Mode) or FM+ mode
|
||||
* 0: FM+ mode
|
||||
* 1: FM mode
|
||||
|
||||
bit[3:0]: device type
|
||||
* 0-15: reserved
|
||||
|
||||
The I2C node unit-address should always match the first cell of the reg
|
||||
property: <device-type>@<i2c-address>.
|
||||
|
||||
I3C devices
|
||||
===========
|
||||
|
||||
All I3C devices are supposed to support DAA (Dynamic Address Assignment), and
|
||||
are thus discoverable. So, by default, I3C devices do not have to be described
|
||||
in the device tree.
|
||||
This being said, one might want to attach extra resources to these devices,
|
||||
and those resources may have to be described in the device tree, which in turn
|
||||
means we have to describe I3C devices.
|
||||
|
||||
Another use case for describing an I3C device in the device tree is when this
|
||||
I3C device has a static I2C address and we want to assign it a specific I3C
|
||||
dynamic address before the DAA takes place (so that other devices on the bus
|
||||
can't take this dynamic address).
|
||||
|
||||
The I3C device should be names <device-type>@<static-i2c-address>,<i3c-pid>,
|
||||
where device-type is describing the type of device connected on the bus
|
||||
(gpio-controller, sensor, ...).
|
||||
|
||||
Required properties
|
||||
-------------------
|
||||
- reg: contains 3 cells
|
||||
+ first cell : encodes the static I2C address. Should be 0 if the device does
|
||||
not have one (0 is not a valid I2C address).
|
||||
|
||||
+ second and third cells: should encode the ProvisionalID. The second cell
|
||||
contains the manufacturer ID left-shifted by 1.
|
||||
The third cell contains ORing of the part ID
|
||||
left-shifted by 16, the instance ID left-shifted
|
||||
by 12 and the extra information. This encoding is
|
||||
following the PID definition provided by the I3C
|
||||
specification.
|
||||
|
||||
Optional properties
|
||||
-------------------
|
||||
- assigned-address: dynamic address to be assigned to this device. This
|
||||
property is only valid if the I3C device has a static
|
||||
address (first cell of the reg property != 0).
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
i3c-master@d040000 {
|
||||
compatible = "cdns,i3c-master";
|
||||
clocks = <&coreclock>, <&i3csysclock>;
|
||||
clock-names = "pclk", "sysclk";
|
||||
interrupts = <3 0>;
|
||||
reg = <0x0d040000 0x1000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
i2c-scl-hz = <100000>;
|
||||
|
||||
/* I2C device. */
|
||||
nunchuk: nunchuk@52 {
|
||||
compatible = "nintendo,nunchuk";
|
||||
reg = <0x52 0x0 0x10>;
|
||||
};
|
||||
|
||||
/* I3C device with a static I2C address. */
|
||||
thermal_sensor: sensor@68,39200144004 {
|
||||
reg = <0x68 0x392 0x144004>;
|
||||
assigned-address = <0xa>;
|
||||
};
|
||||
|
||||
/*
|
||||
* I3C device without a static I2C address but requiring
|
||||
* resources described in the DT.
|
||||
*/
|
||||
sensor@0,39200154004 {
|
||||
reg = <0x0 0x392 0x154004>;
|
||||
clocks = <&clock_provider 0>;
|
||||
};
|
||||
};
|
||||
179
Documentation/devicetree/bindings/i3c/i3c.yaml
Normal file
179
Documentation/devicetree/bindings/i3c/i3c.yaml
Normal file
|
|
@ -0,0 +1,179 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/i3c/i3c.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: I3C bus binding
|
||||
|
||||
maintainers:
|
||||
- Alexandre Belloni <alexandre.belloni@bootlin.com>
|
||||
- Miquel Raynal <miquel.raynal@bootlin.com>
|
||||
|
||||
description: |
|
||||
I3C busses can be described with a node for the primary I3C controller device
|
||||
and a set of child nodes for each I2C or I3C slave on the bus. Each of them
|
||||
may, during the life of the bus, request mastership.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^i3c-master@[0-9a-f]+$"
|
||||
|
||||
"#address-cells":
|
||||
const: 3
|
||||
description: |
|
||||
Each I2C device connected to the bus should be described in a subnode.
|
||||
|
||||
All I3C devices are supposed to support DAA (Dynamic Address Assignment),
|
||||
and are thus discoverable. So, by default, I3C devices do not have to be
|
||||
described in the device tree. This being said, one might want to attach
|
||||
extra resources to these devices, and those resources may have to be
|
||||
described in the device tree, which in turn means we have to describe
|
||||
I3C devices.
|
||||
|
||||
Another use case for describing an I3C device in the device tree is when
|
||||
this I3C device has a static I2C address and we want to assign it a
|
||||
specific I3C dynamic address before the DAA takes place (so that other
|
||||
devices on the bus can't take this dynamic address).
|
||||
|
||||
"#size-cells":
|
||||
const: 0
|
||||
|
||||
i3c-scl-hz:
|
||||
description: |
|
||||
Frequency of the SCL signal used for I3C transfers. When undefined, the
|
||||
default value should be 12.5MHz.
|
||||
|
||||
May not be supported by all controllers.
|
||||
|
||||
i2c-scl-hz:
|
||||
description: |
|
||||
Frequency of the SCL signal used for I2C transfers. When undefined, the
|
||||
default should be to look at LVR (Legacy Virtual Register) values of
|
||||
I2C devices described in the device tree to determine the maximum I2C
|
||||
frequency.
|
||||
|
||||
May not be supported by all controllers.
|
||||
|
||||
required:
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
|
||||
patternProperties:
|
||||
"@[0-9a-f]+$":
|
||||
type: object
|
||||
description: |
|
||||
I2C child, should be named: <device-type>@<i2c-address>
|
||||
|
||||
All properties described in Documentation/devicetree/bindings/i2c/i2c.txt
|
||||
are valid here, except the reg property whose content is changed.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
description:
|
||||
Compatible of the I2C device.
|
||||
|
||||
reg:
|
||||
items:
|
||||
- items:
|
||||
- description: |
|
||||
I2C address. 10 bit addressing is not supported. Devices with
|
||||
10-bit address can't be properly passed through DEFSLVS
|
||||
command.
|
||||
minimum: 0
|
||||
maximum: 0x7f
|
||||
- const: 0
|
||||
- description: |
|
||||
Shall encode the I3C LVR (Legacy Virtual Register):
|
||||
bit[31:8]: unused/ignored
|
||||
bit[7:5]: I2C device index. Possible values:
|
||||
* 0: I2C device has a 50 ns spike filter
|
||||
* 1: I2C device does not have a 50 ns spike filter but
|
||||
supports high frequency on SCL
|
||||
* 2: I2C device does not have a 50 ns spike filter and is
|
||||
not tolerant to high frequencies
|
||||
* 3-7: reserved
|
||||
bit[4]: tell whether the device operates in FM (Fast Mode)
|
||||
or FM+ mode:
|
||||
* 0: FM+ mode
|
||||
* 1: FM mode
|
||||
bit[3:0]: device type
|
||||
* 0-15: reserved
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
"@[0-9a-f]+,[0-9a-f]+$":
|
||||
type: object
|
||||
description: |
|
||||
I3C child, should be named: <device-type>@<static-i2c-address>,<i3c-pid>
|
||||
|
||||
properties:
|
||||
reg:
|
||||
items:
|
||||
- items:
|
||||
- description: |
|
||||
Encodes the static I2C address. Should be 0 if the device does
|
||||
not have one (0 is not a valid I2C address).
|
||||
minimum: 0
|
||||
maximum: 0x7f
|
||||
- description: |
|
||||
First half of the Provisional ID (following the PID
|
||||
definition provided by the I3C specification).
|
||||
|
||||
Contains the manufacturer ID left-shifted by 1.
|
||||
- description: |
|
||||
Second half of the Provisional ID (following the PID
|
||||
definition provided by the I3C specification).
|
||||
|
||||
Contains the ORing of the part ID left-shifted by 16,
|
||||
the instance ID left-shifted by 12 and extra information.
|
||||
|
||||
assigned-address:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0x1
|
||||
maximum: 0xff
|
||||
description: |
|
||||
Dynamic address to be assigned to this device. This property is only
|
||||
valid if the I3C device has a static address (first cell of the reg
|
||||
property != 0).
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
examples:
|
||||
- |
|
||||
i3c-master@d040000 {
|
||||
compatible = "cdns,i3c-master";
|
||||
clocks = <&coreclock>, <&i3csysclock>;
|
||||
clock-names = "pclk", "sysclk";
|
||||
interrupts = <3 0>;
|
||||
reg = <0x0d040000 0x1000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
i2c-scl-hz = <100000>;
|
||||
|
||||
/* I2C device. */
|
||||
nunchuk: nunchuk@52 {
|
||||
compatible = "nintendo,nunchuk";
|
||||
reg = <0x52 0x0 0x10>;
|
||||
};
|
||||
|
||||
/* I3C device with a static I2C address. */
|
||||
thermal_sensor: sensor@68,39200144004 {
|
||||
reg = <0x68 0x392 0x144004>;
|
||||
assigned-address = <0xa>;
|
||||
};
|
||||
|
||||
/*
|
||||
* I3C device without a static I2C address but requiring
|
||||
* resources described in the DT.
|
||||
*/
|
||||
sensor@0,39200154004 {
|
||||
reg = <0x0 0x392 0x154004>;
|
||||
clocks = <&clock_provider 0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -9,6 +9,9 @@ title: MIPI I3C HCI Device Tree Bindings
|
|||
maintainers:
|
||||
- Nicolas Pitre <npitre@baylibre.com>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/i3c/i3c.yaml#
|
||||
|
||||
description: |
|
||||
MIPI I3C Host Controller Interface
|
||||
|
||||
|
|
@ -36,12 +39,14 @@ required:
|
|||
- reg
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
i3c@a0000000 {
|
||||
i3c-master@a0000000 {
|
||||
compatible = "mipi-i3c-hci";
|
||||
reg = <0xa0000000 0x2000>;
|
||||
interrupts = <89>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,60 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/i3c/silvaco,i3c-master.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Silvaco I3C master
|
||||
|
||||
maintainers:
|
||||
- Conor Culhane <conor.culhane@silvaco.com>
|
||||
|
||||
allOf:
|
||||
- $ref: "i3c.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: silvaco,i3c-master-v1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: system clock
|
||||
- description: bus clock
|
||||
- description: other (slower) events clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pclk
|
||||
- const: fast_clk
|
||||
- const: slow_clk
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
examples:
|
||||
- |
|
||||
i3c-master@a0000000 {
|
||||
compatible = "silvaco,i3c-master";
|
||||
clocks = <&zynqmp_clk 71>, <&fclk>, <&sclk>;
|
||||
clock-names = "pclk", "fast_clk", "slow_clk";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 89 4>;
|
||||
reg = <0xa0000000 0x1000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
|
@ -40,6 +40,7 @@ properties:
|
|||
ADC reference voltage supply
|
||||
|
||||
adi,sync-in-gpios:
|
||||
maxItems: 1
|
||||
description:
|
||||
Enables synchronization of multiple devices that require simultaneous
|
||||
sampling. A pulse is always required if the configuration is changed
|
||||
|
|
@ -76,6 +77,7 @@ patternProperties:
|
|||
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: |
|
||||
The channel number.
|
||||
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ properties:
|
|||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
description:
|
||||
Input clock used to derive the sample clock. Expected to be the
|
||||
SoC's APB clock.
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@ properties:
|
|||
description: Power supply for the reference voltage
|
||||
|
||||
reg:
|
||||
description: spi chipselect number according to the usual spi bindings
|
||||
maxItems: 1
|
||||
|
||||
spi-max-frequency:
|
||||
description: maximal spi bus frequency supported
|
||||
|
|
|
|||
|
|
@ -68,6 +68,7 @@ patternProperties:
|
|||
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: |
|
||||
ADC channel number.
|
||||
See include/dt-bindings/iio/qcom,spmi-vadc.h
|
||||
|
|
|
|||
|
|
@ -41,6 +41,8 @@ properties:
|
|||
maxItems: 2
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
description: |
|
||||
Core can use up to two clocks, depending on part used:
|
||||
- "adc" clock: for the analog circuitry, common to all ADCs.
|
||||
|
|
|
|||
|
|
@ -1,16 +1,16 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/iio/dac/adi,ad5686.yaml#
|
||||
$id: http://devicetree.org/schemas/iio/dac/adi,ad5696.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Analog Devices AD5686 and similar multi-channel DACs
|
||||
title: Analog Devices AD5696 and similar multi-channel DACs
|
||||
|
||||
maintainers:
|
||||
- Michael Auchter <michael.auchter@ni.com>
|
||||
|
||||
description: |
|
||||
Binding for Analog Devices AD5686 and similar multi-channel DACs
|
||||
Binding for Analog Devices AD5696 and similar multi-channel DACs
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -48,8 +48,8 @@ examples:
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ad5686: dac@0 {
|
||||
compatible = "adi,ad5686";
|
||||
ad5696: dac@0 {
|
||||
compatible = "adi,ad5696";
|
||||
reg = <0>;
|
||||
vcc-supply = <&dac_vref>;
|
||||
};
|
||||
|
|
@ -11,7 +11,7 @@ maintainers:
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
const: ti,afe4403
|
||||
const: ti,afe4404
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -47,6 +47,7 @@ properties:
|
|||
description: an optional 3x3 mounting rotation matrix.
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
description: |
|
||||
an optional pin needed for AK09911 to set the reset state. This should
|
||||
be usually active low
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@ properties:
|
|||
maxItems: 1
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
description:
|
||||
Active low signal to the AD5272 RESET input.
|
||||
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@ properties:
|
|||
description: touchscreen can be used as a wakeup source.
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
description: reset gpio the chip is connected to.
|
||||
|
||||
vcc33-supply:
|
||||
|
|
|
|||
|
|
@ -69,7 +69,7 @@ properties:
|
|||
- qcom,sm8250-system-noc
|
||||
|
||||
'#interconnect-cells':
|
||||
const: 1
|
||||
enum: [ 1, 2 ]
|
||||
|
||||
qcom,bcm-voters:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ properties:
|
|||
The 1st cell is hw interrupt number, the 2nd cell is channel index.
|
||||
|
||||
clocks:
|
||||
description: ipg clock.
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: ipg
|
||||
|
|
|
|||
|
|
@ -36,6 +36,8 @@ properties:
|
|||
Reference to a phandle of a hardware spinlock provider node.
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
maxItems: 96
|
||||
description:
|
||||
Interrupts references to primary interrupt controller
|
||||
|
||||
|
|
|
|||
|
|
@ -33,6 +33,9 @@ description: |
|
|||
corresponding PRUSS node. The node should be named "interrupt-controller".
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^interrupt-controller@[0-9a-f]+$"
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- ti,pruss-intc
|
||||
|
|
|
|||
|
|
@ -76,7 +76,6 @@ required:
|
|||
- compatible
|
||||
- reg
|
||||
- '#iommu-cells'
|
||||
- power-domains
|
||||
|
||||
oneOf:
|
||||
- required:
|
||||
|
|
@ -86,6 +85,17 @@ oneOf:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
not:
|
||||
contains:
|
||||
const: renesas,ipmmu-vmsa
|
||||
then:
|
||||
required:
|
||||
- power-domains
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r8a7791-cpg-mssr.h>
|
||||
|
|
@ -93,7 +103,7 @@ examples:
|
|||
#include <dt-bindings/power/r8a7791-sysc.h>
|
||||
|
||||
ipmmu_mx: iommu@fe951000 {
|
||||
compatible = "renasas,ipmmu-r8a7791", "renasas,ipmmu-vmsa";
|
||||
compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
|
||||
reg = <0xfe951000 0x1000>;
|
||||
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
|
|||
|
|
@ -69,6 +69,7 @@ patternProperties:
|
|||
if:
|
||||
patternProperties:
|
||||
"^gpio@[0-6]$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
|
|
|
|||
|
|
@ -53,6 +53,7 @@ properties:
|
|||
maxItems: 1
|
||||
|
||||
memory-region:
|
||||
maxItems: 1
|
||||
description:
|
||||
CMA pool to use for buffers allocation instead of the default
|
||||
CMA pool.
|
||||
|
|
|
|||
|
|
@ -40,6 +40,7 @@ properties:
|
|||
Digital core voltage supply, 1.2 volts
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
description: |-
|
||||
Reference to the GPIO connected to the xclr pin, if any.
|
||||
Must be released (set high) after all supplies are applied.
|
||||
|
|
|
|||
|
|
@ -28,6 +28,8 @@ properties:
|
|||
const: 1
|
||||
|
||||
ranges:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
description: |
|
||||
Reflects the memory layout with four integer values per bank. Format:
|
||||
<bank-number> 0 <parent address of bank> <size>
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@ properties:
|
|||
const: "fsl,dpaa2-console"
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: A standard property. Specifies the region where the MCFBA
|
||||
(MC firmware base address) register can be found.
|
||||
|
||||
|
|
|
|||
|
|
@ -40,6 +40,7 @@ properties:
|
|||
There is no card detection available; polling must be used.
|
||||
|
||||
cd-gpios:
|
||||
maxItems: 1
|
||||
description:
|
||||
The card detection will be done using the GPIO provided.
|
||||
|
||||
|
|
@ -104,6 +105,7 @@ properties:
|
|||
line. Not used in combination with eMMC or SDIO.
|
||||
|
||||
wp-gpios:
|
||||
maxItems: 1
|
||||
description:
|
||||
GPIO to use for the write-protect detection.
|
||||
|
||||
|
|
|
|||
|
|
@ -124,7 +124,7 @@ required:
|
|||
if:
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
contains:
|
||||
enum:
|
||||
- renesas,sdhi-r7s72100
|
||||
- renesas,sdhi-r7s9210
|
||||
|
|
|
|||
|
|
@ -1,91 +0,0 @@
|
|||
* SPI NOR flash: ST M25Pxx (and similar) serial flash chips
|
||||
|
||||
Required properties:
|
||||
- #address-cells, #size-cells : Must be present if the device has sub-nodes
|
||||
representing partitions.
|
||||
- compatible : May include a device-specific string consisting of the
|
||||
manufacturer and name of the chip. A list of supported chip
|
||||
names follows.
|
||||
Must also include "jedec,spi-nor" for any SPI NOR flash that can
|
||||
be identified by the JEDEC READ ID opcode (0x9F).
|
||||
|
||||
Supported chip names:
|
||||
at25df321a
|
||||
at25df641
|
||||
at26df081a
|
||||
mr25h128
|
||||
mr25h256
|
||||
mr25h10
|
||||
mr25h40
|
||||
mx25l4005a
|
||||
mx25l1606e
|
||||
mx25l6405d
|
||||
mx25l12805d
|
||||
mx25l25635e
|
||||
n25q064
|
||||
n25q128a11
|
||||
n25q128a13
|
||||
n25q512a
|
||||
s25fl256s1
|
||||
s25fl512s
|
||||
s25sl12801
|
||||
s25fl008k
|
||||
s25fl064k
|
||||
sst25vf040b
|
||||
m25p40
|
||||
m25p80
|
||||
m25p16
|
||||
m25p32
|
||||
m25p64
|
||||
m25p128
|
||||
w25x80
|
||||
w25x32
|
||||
w25q32
|
||||
w25q64
|
||||
w25q32dw
|
||||
w25q80bl
|
||||
w25q128
|
||||
w25q256
|
||||
|
||||
The following chip names have been used historically to
|
||||
designate quirky versions of flash chips that do not support the
|
||||
JEDEC READ ID opcode (0x9F):
|
||||
m25p05-nonjedec
|
||||
m25p10-nonjedec
|
||||
m25p20-nonjedec
|
||||
m25p40-nonjedec
|
||||
m25p80-nonjedec
|
||||
m25p16-nonjedec
|
||||
m25p32-nonjedec
|
||||
m25p64-nonjedec
|
||||
m25p128-nonjedec
|
||||
|
||||
- reg : Chip-Select number
|
||||
- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at
|
||||
|
||||
Optional properties:
|
||||
- m25p,fast-read : Use the "fast read" opcode to read data from the chip instead
|
||||
of the usual "read" opcode. This opcode is not supported by
|
||||
all chips and support for it can not be detected at runtime.
|
||||
Refer to your chips' datasheet to check if this is supported
|
||||
by your chip.
|
||||
- broken-flash-reset : Some flash devices utilize stateful addressing modes
|
||||
(e.g., for 32-bit addressing) which need to be managed
|
||||
carefully by a system. Because these sorts of flash don't
|
||||
have a standardized software reset command, and because some
|
||||
systems don't toggle the flash RESET# pin upon system reset
|
||||
(if the pin even exists at all), there are systems which
|
||||
cannot reboot properly if the flash is left in the "wrong"
|
||||
state. This boolean flag can be used on such systems, to
|
||||
denote the absence of a reliable reset mechanism.
|
||||
|
||||
Example:
|
||||
|
||||
flash: m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,m25p80", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>;
|
||||
m25p,fast-read;
|
||||
};
|
||||
102
Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
Normal file
102
Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
Normal file
|
|
@ -0,0 +1,102 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mtd/jedec,spi-nor.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: SPI NOR flash ST M25Pxx (and similar) serial flash chips
|
||||
|
||||
maintainers:
|
||||
- Rob Herring <robh@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- pattern: "^((((micron|spansion|st),)?\
|
||||
(m25p(40|80|16|32|64|128)|\
|
||||
n25q(32b|064|128a11|128a13|256a|512a|164k)))|\
|
||||
atmel,at25df(321a|641|081a)|\
|
||||
everspin,mr25h(10|40|128|256)|\
|
||||
(mxicy|macronix),mx25l(4005a|1606e|6405d|8005|12805d|25635e)|\
|
||||
(mxicy|macronix),mx25u(4033|4035)|\
|
||||
(spansion,)?s25fl(128s|256s1|512s|008k|064k|164k)|\
|
||||
(sst|microchip),sst25vf(016b|032b|040b)|\
|
||||
(sst,)?sst26wf016b|\
|
||||
(sst,)?sst25wf(040b|080)|\
|
||||
winbond,w25x(80|32)|\
|
||||
(winbond,)?w25q(16|32(w|dw)?|64(dw)?|80bl|128(fw)?|256))$"
|
||||
- const: jedec,spi-nor
|
||||
- items:
|
||||
- enum:
|
||||
- issi,is25lp016d
|
||||
- micron,mt25qu02g
|
||||
- mxicy,mx25r1635f
|
||||
- mxicy,mx25u6435f
|
||||
- mxicy,mx25v8035f
|
||||
- spansion,s25sl12801
|
||||
- spansion,s25fs512s
|
||||
- const: jedec,spi-nor
|
||||
- const: jedec,spi-nor
|
||||
description:
|
||||
Must also include "jedec,spi-nor" for any SPI NOR flash that can be
|
||||
identified by the JEDEC READ ID opcode (0x9F).
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
spi-max-frequency: true
|
||||
spi-rx-bus-width: true
|
||||
spi-tx-bus-width: true
|
||||
|
||||
m25p,fast-read:
|
||||
type: boolean
|
||||
description:
|
||||
Use the "fast read" opcode to read data from the chip instead of the usual
|
||||
"read" opcode. This opcode is not supported by all chips and support for
|
||||
it can not be detected at runtime. Refer to your chips' datasheet to check
|
||||
if this is supported by your chip.
|
||||
|
||||
broken-flash-reset:
|
||||
type: boolean
|
||||
description:
|
||||
Some flash devices utilize stateful addressing modes (e.g., for 32-bit
|
||||
addressing) which need to be managed carefully by a system. Because these
|
||||
sorts of flash don't have a standardized software reset command, and
|
||||
because some systems don't toggle the flash RESET# pin upon system reset
|
||||
(if the pin even exists at all), there are systems which cannot reboot
|
||||
properly if the flash is left in the "wrong" state. This boolean flag can
|
||||
be used on such systems, to denote the absence of a reliable reset
|
||||
mechanism.
|
||||
|
||||
label: true
|
||||
|
||||
partitions:
|
||||
type: object
|
||||
|
||||
'#address-cells': true
|
||||
'#size-cells': true
|
||||
|
||||
patternProperties:
|
||||
# Note: use 'partitions' node for new users
|
||||
'^partition@':
|
||||
type: object
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spansion,m25p80", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>;
|
||||
m25p,fast-read;
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -97,7 +97,7 @@ E.g. below enables Channel 0 alone in the board using External clock
|
|||
as fCAN clock.
|
||||
|
||||
&canfd {
|
||||
pinctrl-0 = <&canfd0_pins &can_clk_pins>;
|
||||
pinctrl-0 = <&canfd0_pins>, <&can_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
|
|
|
|||
|
|
@ -206,6 +206,11 @@ properties:
|
|||
Indicates that full-duplex is used. When absent, half
|
||||
duplex is assumed.
|
||||
|
||||
pause:
|
||||
$ref: /schemas/types.yaml#definitions/flag
|
||||
description:
|
||||
Indicates that pause should be enabled.
|
||||
|
||||
asym-pause:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
|
|
|
|||
|
|
@ -72,6 +72,7 @@ properties:
|
|||
dma-coherent: true
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
description: CPSWxG NUSS functional clock
|
||||
|
||||
clock-names:
|
||||
|
|
|
|||
|
|
@ -59,6 +59,7 @@ properties:
|
|||
- const: cpts
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
description: CPTS reference clock
|
||||
|
||||
clock-names:
|
||||
|
|
|
|||
|
|
@ -51,9 +51,11 @@ properties:
|
|||
- const: usb2_reset
|
||||
|
||||
usb0_id_det-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO to the USB OTG ID pin
|
||||
|
||||
usb0_vbus_det-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO to the USB OTG VBUS detect pin
|
||||
|
||||
usb0_vbus_power-supply:
|
||||
|
|
|
|||
|
|
@ -50,9 +50,11 @@ properties:
|
|||
- const: usb1_reset
|
||||
|
||||
usb0_id_det-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO to the USB OTG ID pin
|
||||
|
||||
usb0_vbus_det-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO to the USB OTG VBUS detect pin
|
||||
|
||||
usb0_vbus_power-supply:
|
||||
|
|
|
|||
|
|
@ -50,9 +50,11 @@ properties:
|
|||
- const: usb3_reset
|
||||
|
||||
usb0_id_det-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO to the USB OTG ID pin
|
||||
|
||||
usb0_vbus_det-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO to the USB OTG VBUS detect pin
|
||||
|
||||
usb0_vbus_power-supply:
|
||||
|
|
|
|||
|
|
@ -45,9 +45,11 @@ properties:
|
|||
- const: usb1_reset
|
||||
|
||||
usb0_id_det-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO to the USB OTG ID pin
|
||||
|
||||
usb0_vbus_det-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO to the USB OTG VBUS detect pin
|
||||
|
||||
usb0_vbus_power-supply:
|
||||
|
|
|
|||
|
|
@ -54,9 +54,11 @@ properties:
|
|||
- const: usb2_reset
|
||||
|
||||
usb0_id_det-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO to the USB OTG ID pin
|
||||
|
||||
usb0_vbus_det-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO to the USB OTG VBUS detect pin
|
||||
|
||||
usb0_vbus_power-supply:
|
||||
|
|
|
|||
|
|
@ -50,9 +50,11 @@ properties:
|
|||
- const: usb1_reset
|
||||
|
||||
usb0_id_det-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO to the USB OTG ID pin
|
||||
|
||||
usb0_vbus_det-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO to the USB OTG VBUS detect pin
|
||||
|
||||
usb0_vbus_power-supply:
|
||||
|
|
|
|||
|
|
@ -56,9 +56,11 @@ properties:
|
|||
- const: usb2_reset
|
||||
|
||||
usb0_id_det-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO to the USB OTG ID pin
|
||||
|
||||
usb0_vbus_det-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO to the USB OTG VBUS detect pin
|
||||
|
||||
usb0_vbus_power-supply:
|
||||
|
|
|
|||
|
|
@ -62,9 +62,11 @@ properties:
|
|||
- const: usb3_reset
|
||||
|
||||
usb0_id_det-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO to the USB OTG ID pin
|
||||
|
||||
usb0_vbus_det-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO to the USB OTG VBUS detect pin
|
||||
|
||||
usb0_vbus_power-supply:
|
||||
|
|
|
|||
|
|
@ -56,9 +56,11 @@ properties:
|
|||
- const: usb2_reset
|
||||
|
||||
usb0_id_det-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO to the USB OTG ID pin
|
||||
|
||||
usb0_vbus_det-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO to the USB OTG VBUS detect pin
|
||||
|
||||
usb0_vbus_power-supply:
|
||||
|
|
|
|||
|
|
@ -42,9 +42,11 @@ properties:
|
|||
const: usb0_reset
|
||||
|
||||
usb0_id_det-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO to the USB OTG ID pin
|
||||
|
||||
usb0_vbus_det-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO to the USB OTG VBUS detect pin
|
||||
|
||||
usb0_vbus_power-supply:
|
||||
|
|
|
|||
|
|
@ -22,7 +22,8 @@ properties:
|
|||
|
||||
clocks:
|
||||
anyOf:
|
||||
- description: Main PHY Clock
|
||||
- maxItems: 1
|
||||
description: Main PHY Clock
|
||||
|
||||
- items:
|
||||
- description: Main PHY clock
|
||||
|
|
@ -39,20 +40,16 @@ properties:
|
|||
- const: hsic_480M
|
||||
|
||||
resets:
|
||||
anyOf:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: Normal USB PHY reset
|
||||
|
||||
- items:
|
||||
- description: Normal USB PHY reset
|
||||
- description: HSIC Reset
|
||||
- description: HSIC Reset
|
||||
|
||||
reset-names:
|
||||
oneOf:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: phy
|
||||
|
||||
- items:
|
||||
- const: phy
|
||||
- const: hsic
|
||||
- const: hsic
|
||||
|
||||
phy_type:
|
||||
const: hsic
|
||||
|
|
|
|||
|
|
@ -99,8 +99,7 @@ patternProperties:
|
|||
if:
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
const: brcm,iproc-ns2-sata-phy
|
||||
const: brcm,iproc-ns2-sata-phy
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
|
|
|
|||
|
|
@ -81,9 +81,8 @@ properties:
|
|||
if:
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
enum:
|
||||
- renesas,usb2-phy-r7s9210
|
||||
contains:
|
||||
const: renesas,usb2-phy-r7s9210
|
||||
then:
|
||||
required:
|
||||
- clock-names
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user