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mmc: dw_mmc-rockchip: Add memory clock auto-gating support

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Per design recommendations, the memory clock can be gated when there
is no in-flight transfer, which helps save power. This feature is
introduced alongside internal phase support, and this patch enables it.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Shawn Lin 2025-11-04 15:41:34 +08:00 committed by Ulf Hansson
parent 93daf13303
commit ff6f0286c8
1 changed files with 6 additions and 0 deletions
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6
drivers/mmc/host/dw_mmc-rockchip.c
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@ -19,6 +19,8 @@
#define RK3288_CLKGEN_DIV 2 #define RK3288_CLKGEN_DIV 2
#define SDMMC_TIMING_CON0 0x130 #define SDMMC_TIMING_CON0 0x130
#define SDMMC_TIMING_CON1 0x134 #define SDMMC_TIMING_CON1 0x134
#define SDMMC_MISC_CON 0x138
#define MEM_CLK_AUTOGATE_ENABLE BIT(5)
#define ROCKCHIP_MMC_DELAY_SEL BIT(10) #define ROCKCHIP_MMC_DELAY_SEL BIT(10)
#define ROCKCHIP_MMC_DEGREE_MASK 0x3 #define ROCKCHIP_MMC_DEGREE_MASK 0x3
#define ROCKCHIP_MMC_DEGREE_OFFSET 1 #define ROCKCHIP_MMC_DEGREE_OFFSET 1
@ -470,6 +472,7 @@ static int dw_mci_rk3576_parse_dt(struct dw_mci *host)
static int dw_mci_rockchip_init(struct dw_mci *host) static int dw_mci_rockchip_init(struct dw_mci *host)
{ {
struct dw_mci_rockchip_priv_data *priv = host->priv;
int ret, i; int ret, i;
/* It is slot 8 on Rockchip SoCs */ /* It is slot 8 on Rockchip SoCs */
@ -494,6 +497,9 @@ static int dw_mci_rockchip_init(struct dw_mci *host)
dev_warn(host->dev, "no valid minimum freq: %d\n", ret); dev_warn(host->dev, "no valid minimum freq: %d\n", ret);
} }
if (priv->internal_phase)
mci_writel(host, MISC_CON, MEM_CLK_AUTOGATE_ENABLE);
return 0; return 0;
} }