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ARM: dts: rockchip: amend usb and phy properties for rv1126

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Change-Id: I99e27c05f8d7372d922480bb4d3199101b71f7d7
Signed-off-by: Jianing Ren <jianing.ren@rock-chips.com>
This commit is contained in:
Jianing Ren 2020-03-31 09:09:53 +08:00 committed by Tao Huang
parent 004b4e8245
commit ff3f8c24fc
1 changed files with 7 additions and 4 deletions
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11
arch/arm/boot/dts/rv1126.dtsi
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@ -770,12 +770,12 @@ csi_dphy1: csi-dphy@ff4b8000 {
u2phy0: usb2-phy@ff4c0000 {
compatible = "rockchip,rv1126-usb2phy";
reg = <0xff4c0000 0x8000>;
rockchip,grf = <&grf>;
clocks = <&pmucru CLK_USBPHY_OTG_REF>, <&cru PCLK_USBPHY_OTG>;
clock-names = "phyclk", "pclk";
resets = <&cru SRST_USBPHYPOR_OTG>, <&cru SRST_USBPHY_OTG_P>;
reset-names = "u2phy", "u2phy-apb";
#clock-cells = <0>;
clock-output-names = "usb480m_phy0";
status = "disabled";
u2phy_otg: otg-port {
@ -793,12 +793,15 @@ u2phy_otg: otg-port {
u2phy1: usb2-phy@ff4c8000 {
compatible = "rockchip,rv1126-usb2phy";
reg = <0xff4c8000 0x8000>;
rockchip,grf = <&grf>;
clocks = <&pmucru CLK_USBPHY_HOST_REF>, <&cru PCLK_USBPHY_HOST>;
clock-names = "phyclk", "pclk";
assigned-clocks = <&cru USB480M>;
assigned-clock-parents = <&u2phy1>;
resets = <&cru SRST_USBPHYPOR_HOST>, <&cru SRST_USBPHY_HOST_P>;
reset-names = "u2phy", "u2phy-apb";
#clock-cells = <0>;
clock-output-names = "usb480m_phy1";
clock-output-names = "usb480m_phy";
status = "disabled";
u2phy_host: host-port {
@ -1728,7 +1731,7 @@ usbdrd_dwc3: dwc3@ffd00000 {
usb_host0_ehci: usb@ffe00000 {
compatible = "generic-ehci";
reg = <0xffe00000 0x20000>;
reg = <0xffe00000 0x10000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>,
<&u2phy1>;
@ -1741,7 +1744,7 @@ usb_host0_ehci: usb@ffe00000 {
usb_host0_ohci: usb@ffe10000 {
compatible = "generic-ohci";
reg = <0xffe20000 0x20000>;
reg = <0xffe10000 0x10000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>,
<&u2phy1>;