arm64: dts: ti: k3-{am62p,j722s}: Disable ethernet by default

Device tree best practice is to disable any external interface in the
dtsi and just enable them if needed in the device tree. Thus, disable
the ethernet switch and its ports by default and just enable the ones
used by the EVMs in their device trees.

There is no functional change.

Signed-off-by: Michael Walle <mwalle@kernel.org>
Acked-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20240403101545.3932437-1-mwalle@kernel.org
Signed-off-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
Michael Walle 2024-04-03 12:15:45 +02:00 committed by Nishanth Menon
parent 853d39f96c
commit ff369c9eb6
3 changed files with 7 additions and 4 deletions

View File

@ -673,6 +673,7 @@ cpsw3g: ethernet@8000000 {
assigned-clock-parents = <&k3_clks 13 11>;
clock-names = "fck";
power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
dmas = <&main_pktdma 0xc600 15>,
<&main_pktdma 0xc601 15>,
@ -696,6 +697,7 @@ cpsw_port1: port@1 {
label = "port1";
phys = <&phy_gmii_sel 1>;
mac-address = [00 00 00 00 00 00];
status = "disabled";
};
cpsw_port2: port@2 {
@ -704,6 +706,7 @@ cpsw_port2: port@2 {
label = "port2";
phys = <&phy_gmii_sel 2>;
mac-address = [00 00 00 00 00 00];
status = "disabled";
};
};

View File

@ -431,16 +431,19 @@ &cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&main_rgmii1_pins_default>,
<&main_rgmii2_pins_default>;
status = "okay";
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
status = "okay";
};
&cpsw_port2 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy1>;
status = "okay";
};
&cpsw3g_mdio {

View File

@ -226,10 +226,7 @@ cpsw3g_phy0: ethernet-phy@0 {
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
};
&cpsw_port2 {
status = "disabled";
status = "okay";
};
&main_gpio1 {