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This pull request contains Broadcom ARM64-based SoCs Device Tree updates
for 6.16, please pull the following: - Stanimir adds and enables the PCIe root complex Device Tree nodes present on the Raspberry Pi 5 - Rob updates the BCM2712 L2 cache node names to use a more comforming name -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAmgY7C0ACgkQh9CWnEQH BwTvpxAAjAWMHd8lDmxLaqEEbnrxwkFVaohY4dre3YY10LLfGGGboGxSQ9zhdeh5 FZxRo3wSlPSJZnQuFDcO9+ww7YQy+0qXsf09/EhWqx9y/Pqt3TqeKD8IXGOMrwNC lF7znyZGXsYDC3Cg8t0fFn3lLZKp50Crl4PEVqVqX0nrPZJFe4VnMx1yO/Tq724B ZFBd2EoA1csA3FKRLP8TNpeKdyITwLZIllQZAuVHaj7vPDw7GYNFAS38L6chNUPH ogSZGKRS9B0u9rVkXfiZZsl3PheK4duCVfn2Kc3oLi5OorRIzFbujJMyvHs0N7zW V65MkU6iANg0SuL9NdBndCxQtAik+qojG0L33+nUif8+4wgcV/8ude99rl24Zlce sJz7xnygQafP5MnVF2QeUl5DLVKUMOoErfBsOAr3UQMpu5FQk4HnW1yuSRyC/S08 /BQv7mxwy67ildEtGZ5qPdGk17ni4VtWbIEozE/kXKSJa2WzDneDe4LwVB296h9Q WVDQLWnMCFxAOG1G3NKLpLU0x92pHTPraMu21kEqmedsPCt8tlKeto31f9g325jp eRLJqWP/zhdhAi5OmP6tfHrQIuILkMrpg5kiJh9gn8SWnwevy1r0rwV1BFV9Vik9 T7Ei3j7J8tI2ifknm2ST3usp3n7IbxFba2gbiSMeehk9tyMF30E= =mbv6 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmgeaRUACgkQYKtH/8kJ UietQw//a+2EzRI6Qr+ufF1EbQaqUvEjAyfBl1msG/ODDdMMgH6Oph61JUdHJtXB EUHi6kBSTHQuzpE/hB0rqXQp67cvPdQALTVd1D6Wt09h7e2rfB817dtbJZQA5VG7 uQRVPxwxJS8Zh6hsu1kHRIK8zGKqoK0dNV8/SDpgGU4M/xdhlU2ub+8VoJREwY1a NdPBncBqZhd4v+6dflDSL17QbERzG8LvUEatWI+IhKH2a68Sj1iO4+okgXiYSIe8 5saNzZfNrn156CDYu2vV9NNKyar+2xcSubZvEUJt4AcaZScXLTst31yPi+wKolNr ZUCy+IHSLXk4sKwHLantjth5cyR4GiJyrz3Qx224e01GreCU/H628mBlnsHWXan7 tTPE/cNnbm/y3JjyQ1iIt/ft11NWf+5wfafi23mhmwyP9rmRt2hilfqZ/W5ok+ft ILHffI7AE9bkT0fe8gLwoKUcgmZtazvVkiuph0JHxRHhJSiVl2SxrbJgB7ABYclK iwtYaG2TKg9o6oZdDpjjBMM9KEJBvbfKlSUZ808sPePg9nql/vIg3yceqxr42Bct 1DA0J1U6bWnQfD8tXWkNdhzu9E6MrI2RDQrMEIjivg1ztSuXKHBxh4ekaTMCLnMD kolX9xv6N36PbyYT7h5kTHZzEmuqnMQ3XsHODbYD/FVBw4iNnac= =QRDp -----END PGP SIGNATURE----- Merge tag 'arm-soc/for-6.16/devicetree-arm64' of https://github.com/Broadcom/stblinux into soc/dt This pull request contains Broadcom ARM64-based SoCs Device Tree updates for 6.16, please pull the following: - Stanimir adds and enables the PCIe root complex Device Tree nodes present on the Raspberry Pi 5 - Rob updates the BCM2712 L2 cache node names to use a more comforming name * tag 'arm-soc/for-6.16/devicetree-arm64' of https://github.com/Broadcom/stblinux: arm64: dts: broadcom: bcm2712: Use "l2-cache" for L2 cache node names arm64: dts: broadcom: bcm2712-rpi-5-b: Enable PCIe DT nodes arm64: dts: broadcom: bcm2712: Add PCIe DT nodes Link: https://lore.kernel.org/r/20250505165810.1948927-2-florian.fainelli@broadcom.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
fecf15fab3
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@ -104,3 +104,11 @@ &hdmi1 {
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clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;
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clock-names = "hdmi", "bvb", "audio", "cec";
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};
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&pcie1 {
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status = "okay";
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};
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&pcie2 {
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status = "okay";
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};
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@ -64,7 +64,7 @@ cpu0: cpu@0 {
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i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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next-level-cache = <&l2_cache_l0>;
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l2_cache_l0: l2-cache-l0 {
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l2_cache_l0: l2-cache {
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compatible = "cache";
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cache-size = <0x80000>;
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cache-line-size = <64>;
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@ -88,7 +88,7 @@ cpu1: cpu@1 {
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i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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next-level-cache = <&l2_cache_l1>;
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l2_cache_l1: l2-cache-l1 {
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l2_cache_l1: l2-cache {
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compatible = "cache";
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cache-size = <0x80000>;
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cache-line-size = <64>;
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@ -112,7 +112,7 @@ cpu2: cpu@2 {
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i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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next-level-cache = <&l2_cache_l2>;
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l2_cache_l2: l2-cache-l2 {
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l2_cache_l2: l2-cache {
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compatible = "cache";
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cache-size = <0x80000>;
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cache-line-size = <64>;
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@ -136,7 +136,7 @@ cpu3: cpu@3 {
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i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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next-level-cache = <&l2_cache_l3>;
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l2_cache_l3: l2-cache-l3 {
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l2_cache_l3: l2-cache {
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compatible = "cache";
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cache-size = <0x80000>;
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cache-line-size = <64>;
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@ -192,6 +192,12 @@ soc: soc@107c000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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pcie_rescal: reset-controller@119500 {
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compatible = "brcm,bcm7216-pcie-sata-rescal";
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reg = <0x00119500 0x10>;
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#reset-cells = <0>;
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};
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sdio1: mmc@fff000 {
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compatible = "brcm,bcm2712-sdhci",
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"brcm,sdhci-brcmstb";
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@ -204,6 +210,12 @@ sdio1: mmc@fff000 {
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mmc-ddr-3_3v;
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};
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bcm_reset: reset-controller@1504318 {
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compatible = "brcm,brcmstb-reset";
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reg = <0x01504318 0x30>;
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#reset-cells = <1>;
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};
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system_timer: timer@7c003000 {
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compatible = "brcm,bcm2835-system-timer";
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reg = <0x7c003000 0x1000>;
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@ -426,6 +438,141 @@ axi: axi {
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vc4: gpu {
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compatible = "brcm,bcm2712-vc6";
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};
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pcie0: pcie@1000100000 {
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compatible = "brcm,bcm2712-pcie";
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reg = <0x10 0x00100000 0x00 0x9310>;
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device_type = "pci";
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linux,pci-domain = <0>;
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max-link-speed = <2>;
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num-lanes = <1>;
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#address-cells = <3>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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interrupt-parent = <&gicv2>;
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interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pcie", "msi";
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &gicv2 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &gicv2 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &gicv2 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&pcie_rescal>, <&bcm_reset 42>;
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reset-names = "rescal", "bridge";
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msi-controller;
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msi-parent = <&pcie0>;
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ranges =
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/* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
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<0x02000000 0x00 0x00000000 0x17 0x00000000 0x00 0xfffffffc>,
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/* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */
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<0x43000000 0x04 0x00000000 0x14 0x00000000 0x03 0x00000000>;
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dma-ranges =
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/* 64GiB, 64-bit, prefetchable at PCIe 10_0000_0000 */
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<0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>;
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status = "disabled";
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};
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pcie1: pcie@1000110000 {
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compatible = "brcm,bcm2712-pcie";
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reg = <0x10 0x00110000 0x00 0x9310>;
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device_type = "pci";
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linux,pci-domain = <1>;
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max-link-speed = <2>;
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num-lanes = <1>;
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#address-cells = <3>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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interrupt-parent = <&gicv2>;
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interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pcie", "msi";
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &gicv2 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &gicv2 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &gicv2 GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&pcie_rescal>, <&bcm_reset 43>;
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reset-names = "rescal", "bridge";
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msi-controller;
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msi-parent = <&mip1>;
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ranges =
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/* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
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<0x02000000 0x00 0x00000000 0x1b 0x00000000 0x00 0xfffffffc>,
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/* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */
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<0x43000000 0x04 0x00000000 0x18 0x00000000 0x03 0x00000000>;
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dma-ranges =
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/* 64GiB, 64-bit, non-prefetchable at PCIe 10_0000_0000 */
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<0x03000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>,
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/* 4KiB, 64-bit, non-prefetchable at PCIe ff_ffff_f000 MIP1 */
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<0x03000000 0xff 0xfffff000 0x10 0x00131000 0x00 0x00001000>;
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status = "disabled";
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};
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pcie2: pcie@1000120000 {
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compatible = "brcm,bcm2712-pcie";
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reg = <0x10 0x00120000 0x00 0x9310>;
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device_type = "pci";
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linux,pci-domain = <2>;
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max-link-speed = <2>;
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num-lanes = <4>;
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#address-cells = <3>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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interrupt-parent = <&gicv2>;
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interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pcie", "msi";
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &gicv2 GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &gicv2 GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &gicv2 GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&pcie_rescal>, <&bcm_reset 44>;
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reset-names = "rescal", "bridge";
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msi-controller;
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msi-parent = <&mip0>;
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ranges =
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/* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
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<0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0xfffffffc>,
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/* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */
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<0x43000000 0x04 0x00000000 0x1c 0x00000000 0x03 0x00000000>;
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dma-ranges =
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/* 4MiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
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<0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0x00400000>,
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/* 64GiB, 64-bit, prefetchable at PCIe 10_0000_0000 */
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<0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>,
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/* 4KiB, 64-bit, non-prefetchable at PCIe ff_ffff_f000 MIP0 */
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<0x03000000 0xff 0xfffff000 0x10 0x00130000 0x00 0x00001000>;
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status = "disabled";
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};
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mip0: msi-controller@1000130000 {
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compatible = "brcm,bcm2712-mip";
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reg = <0x10 0x00130000 0x00 0xc0>,
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<0xff 0xfffff000 0x00 0x1000>;
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msi-controller;
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msi-ranges = <&gicv2 GIC_SPI 128 IRQ_TYPE_EDGE_RISING 64>;
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brcm,msi-offset = <0>;
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};
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mip1: msi-controller@1000131000 {
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compatible = "brcm,bcm2712-mip";
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reg = <0x10 0x00131000 0x00 0xc0>,
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<0xff 0xfffff000 0x00 0x1000>;
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msi-controller;
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msi-ranges = <&gicv2 GIC_SPI 247 IRQ_TYPE_EDGE_RISING 8>;
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brcm,msi-offset = <8>;
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};
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};
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timer {
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