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drm/amdgpu/gfx11: enable gfx pipe1 hardware support

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Enable gfx pipe1 hardware support.  This is only available
on gfx11 chips using the F32 microcontroller.  Chips using
the RS64 microcontroller are not able to use the second gfx
pipe.  In practice this means the second pipe is only
available on APUs. This explains the stability issues
Pierre-Eric saw previously with this on Navi33.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2026-02-03 11:31:48 -05:00
parent 402ebe22b2
commit fec62b5e14
1 changed files with 17 additions and 5 deletions
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22
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
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@ -51,7 +51,7 @@
#include "mes_userqueue.h"
#include "amdgpu_userq_fence.h"
#define GFX11_NUM_GFX_RINGS 1
#define GFX11_NUM_GFX_RINGS 2
#define GFX11_MEC_HPD_SIZE 2048
#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
@ -1625,7 +1625,10 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
case IP_VERSION(11, 7, 0):
case IP_VERSION(11, 7, 1):
adev->gfx.me.num_me = 1;
adev->gfx.me.num_pipe_per_me = 1;
if (adev->gfx.rs64_enable)
adev->gfx.me.num_pipe_per_me = 1;
else
adev->gfx.me.num_pipe_per_me = 2;
adev->gfx.me.num_queue_per_pipe = 2;
adev->gfx.mec.num_mec = 1;
adev->gfx.mec.num_pipe_per_mec = 4;
@ -5366,6 +5369,7 @@ static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
static int gfx_v11_0_early_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
int r;
switch (amdgpu_user_queue) {
case -1:
@ -5386,6 +5390,11 @@ static int gfx_v11_0_early_init(struct amdgpu_ip_block *ip_block)
adev->gfx.funcs = &gfx_v11_0_gfx_funcs;
gfx_v11_0_set_imu_funcs(adev);
r = gfx_v11_0_init_microcode(adev);
if (r)
return r;
if (adev->gfx.disable_kq) {
/* We need one GFX ring temporarily to set up
* the clear state.
@ -5393,7 +5402,11 @@ static int gfx_v11_0_early_init(struct amdgpu_ip_block *ip_block)
adev->gfx.num_gfx_rings = 1;
adev->gfx.num_compute_rings = 0;
} else {
adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS;
/* rs64 only supports one gfx pipe */
if (adev->gfx.rs64_enable)
adev->gfx.num_gfx_rings = 1;
else
adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS;
adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
AMDGPU_MAX_COMPUTE_RINGS);
}
@ -5404,13 +5417,12 @@ static int gfx_v11_0_early_init(struct amdgpu_ip_block *ip_block)
gfx_v11_0_set_gds_init(adev);
gfx_v11_0_set_rlc_funcs(adev);
gfx_v11_0_set_mqd_funcs(adev);
gfx_v11_0_set_imu_funcs(adev);
gfx_v11_0_init_rlcg_reg_access_ctrl(adev);
amdgpu_init_rlc_reg_funcs(adev);
return gfx_v11_0_init_microcode(adev);
return 0;
}
static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev)