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drm/amd/display: Add SMU timeout check and retry
Instead of only asserting in the case of the SMU wait time is not what we expect, add the SMU timeout check and try again. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -26,6 +26,10 @@
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#include "core_types.h"
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#include "clk_mgr_internal.h"
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#include "reg_helper.h"
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#include "dm_helpers.h"
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#include "rn_clk_mgr_vbios_smu.h"
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#include <linux/delay.h>
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#include "renoir_ip_offset.h"
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@ -33,8 +37,6 @@
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#include "mp/mp_12_0_0_offset.h"
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#include "mp/mp_12_0_0_sh_mask.h"
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#include "rn_clk_mgr_vbios_smu.h"
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#define REG(reg_name) \
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(MP0_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
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@ -120,7 +122,10 @@ static int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
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result = rn_smu_wait_for_response(clk_mgr, 10, 200000);
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ASSERT(result == VBIOSSMC_Result_OK || result == VBIOSSMC_Result_UnknownCmd);
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if (IS_SMU_TIMEOUT(result)) {
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ASSERT(0);
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dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 200000);
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}
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/* Actual dispclk set is returned in the parameter register */
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return REG_READ(MP1_SMN_C2PMSG_83);
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@ -29,6 +29,7 @@
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#include <linux/delay.h>
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#include "dcn301_smu.h"
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#include "dm_helpers.h"
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#include "vangogh_ip_offset.h"
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@ -120,7 +121,10 @@ static int dcn301_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
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result = dcn301_smu_wait_for_response(clk_mgr, 10, 200000);
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ASSERT(result == VBIOSSMC_Result_OK);
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if (IS_SMU_TIMEOUT(result)) {
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ASSERT(0);
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dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 200000);
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}
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/* Actual dispclk set is returned in the parameter register */
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return REG_READ(MP1_SMN_C2PMSG_83);
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