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clk: qcom: cpu-8996: support using GPLL0 as SMUX input

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In some cases the driver might need using GPLL0 to drive CPU clocks.
Bring it in through the sys_apcs_aux clock.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230113120544.59320-6-dmitry.baryshkov@linaro.org
This commit is contained in:
Dmitry Baryshkov 2023-01-13 14:05:35 +02:00 committed by Bjorn Andersson
parent be4e65d130
commit fe8a500534
1 changed files with 12 additions and 0 deletions
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12
drivers/clk/qcom/clk-cpu-8996.c
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@ -12,6 +12,8 @@
* +-------+
* XO | |
* +------------------>0 |
* SYS_APCS_AUX | |
* +------------------>3 |
* | |
* PLL/2 | SMUX +----+
* +------->1 | |
@ -310,20 +312,29 @@ static const struct clk_ops clk_cpu_8996_pmux_ops = {
.determine_rate = clk_cpu_8996_pmux_determine_rate,
};
static const struct parent_map smux_parent_map[] = {
{ .cfg = 0, }, /* xo */
{ .cfg = 1, }, /* pll */
{ .cfg = 3, }, /* sys_apcs_aux */
};
static const struct clk_parent_data pwrcl_smux_parents[] = {
{ .fw_name = "xo" },
{ .hw = &pwrcl_pll_postdiv.hw },
{ .fw_name = "sys_apcs_aux" },
};
static const struct clk_parent_data perfcl_smux_parents[] = {
{ .fw_name = "xo" },
{ .hw = &perfcl_pll_postdiv.hw },
{ .fw_name = "sys_apcs_aux" },
};
static struct clk_regmap_mux pwrcl_smux = {
.reg = PWRCL_REG_OFFSET + MUX_OFFSET,
.shift = 2,
.width = 2,
.parent_map = smux_parent_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "pwrcl_smux",
.parent_data = pwrcl_smux_parents,
@ -337,6 +348,7 @@ static struct clk_regmap_mux perfcl_smux = {
.reg = PERFCL_REG_OFFSET + MUX_OFFSET,
.shift = 2,
.width = 2,
.parent_map = smux_parent_map,
.clkr.hw.init = &(struct clk_init_data) {
.name = "perfcl_smux",
.parent_data = perfcl_smux_parents,