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arm64: dts: exynos: add secondary ufs devices in ExynosAutov9

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Add ufs_1_phy and ufs_1 for secondary ufs hci controller and phy
device.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Link: https://lore.kernel.org/r/20220607070251.15795-2-chanho61.park@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Chanho Park 2022-06-07 16:02:50 +09:00 committed by Krzysztof Kozlowski
parent 5621638cf0
commit fddb792846
1 changed files with 32 additions and 0 deletions
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32
arch/arm64/boot/dts/exynos/exynosautov9.dtsi
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@ -401,6 +401,38 @@ ufs_0: ufs@17e00000 {
status = "disabled";
};
ufs_1_phy: phy@17f04000 {
compatible = "samsung,exynosautov9-ufs-phy";
reg = <0x17f04000 0xc00>;
reg-names = "phy-pma";
samsung,pmu-syscon = <&pmu_system_controller 0x72c>;
#phy-cells = <0>;
clocks = <&xtcxo>;
clock-names = "ref_clk";
status = "disabled";
};
ufs_1: ufs@17f00000 {
compatible = "samsung,exynosautov9-ufs";
reg = <0x17f00000 0x100>,
<0x17f01100 0x410>,
<0x17f80000 0x8000>,
<0x17de0000 0x2200>;
reg-names = "hci", "vs_hci", "unipro", "ufsp";
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_ACLK>,
<&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO>;
clock-names = "core_clk", "sclk_unipro_main";
freq-table-hz = <0 0>, <0 0>;
pinctrl-names = "default";
pinctrl-0 = <&ufs_rst_n_1 &ufs_refclk_out_1>;
phys = <&ufs_1_phy>;
phy-names = "ufs-phy";
samsung,sysreg = <&syscon_fsys2 0x714>;
status = "disabled";
};
watchdog_cl0: watchdog@10050000 {
compatible = "samsung,exynosautov9-wdt";
reg = <0x10050000 0x100>;