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Mediatek DRM Fixes - 20250104
1. Revert "drm/mediatek: dsi: Correct calculation formula of PHY Timing" 2. Set private->all_drm_private[i]->drm to NULL if mtk_drm_bind returns err 3. Move mtk_crtc_finish_page_flip() to ddp_cmdq_cb() 4. Only touch DISP_REG_OVL_PITCH_MSB if AFBC is supported 5. Add support for 180-degree rotation in the display driver 6. Stop selecting foreign drivers 7. Revert "drm/mediatek: Switch to for_each_child_of_node_scoped()" 8. Fix YCbCr422 color format issue for DP 9. Fix mode valid issue for dp 10. dp: Reference common DAI properties 11. dsi: Add registers to pdata to fix MT8186/MT8188 12. Remove unneeded semicolon 13. Add return value check when reading DPCD 14. Initialize pointer in mtk_drm_of_ddp_path_build_one() -----BEGIN PGP SIGNATURE----- iQJMBAABCgA2FiEEACwLKSDmq+9RDv5P4cpzo8lZTiQFAmd5KnMYHGNodW5rdWFu Zy5odUBrZXJuZWwub3JnAAoJEOHKc6PJWU4knsAP/3/WLT3sNSvlrT2t4AwMwrgt jSFV1jtiDpEaPF8+tlg0BdE1CTqkCQOCOZMBKYvsUEifAT7MDBdfIAWBMZbpRRh/ ptvHw1vBEBQpAkmo2hPJfK+J1BDncpqh65A+C1TFiBG5XKv9Zp5QXShBfZsdmqYO zfWKJ4pfUnvUgwM0RQhdRws5S45mbDqGtENiL/8MZXyouOyawqzt6hDSqSglJ+h9 NaWD+607dmAzkMYaGe35gvTsFpxV/8euNWxskbciH/vm33mBm95hsymQOKP7spuq XmKq+mbRa+mZgBGznT+MdyGwHBN0h/yrv1mHUDoi5O5MFQJ4kDuRB/c5bVG1FAoN 4AQLEv6TXhAMZWlf3LOGGVgwEO8mG+7mNF7dXMckMgNCQAZVKfaPIyoFgHn29+6g Dnom/LIOQzP65x0ta5ihCaH//6e7QCsVOWvQnqfn3JUlwtYv2NTjYu6l8+RO+kFS 2/WP4hOpJlqjESiEMoRSpbriYN3dCI64OY4mNB7pr0ea8YtPehE09uzvHSmfDbGe GT+9lWsYblTFTkZXJdthUC39v0grJh4QTKBWNldAaqGsS3hItsuDHOrGlLFJwtSx 9tXlQR27XOJVt0hfRKJMiONW2xXW2sNUnlt3kA7qPmH+zjdeo3vKxlCBYzISKepI kg4CeI6clR9ocZkTPa/0 =bc7g -----END PGP SIGNATURE----- Merge tag 'mediatek-drm-fixes-20250104' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-fixes Mediatek DRM Fixes - 20250104 1. Revert "drm/mediatek: dsi: Correct calculation formula of PHY Timing" 2. Set private->all_drm_private[i]->drm to NULL if mtk_drm_bind returns err 3. Move mtk_crtc_finish_page_flip() to ddp_cmdq_cb() 4. Only touch DISP_REG_OVL_PITCH_MSB if AFBC is supported 5. Add support for 180-degree rotation in the display driver 6. Stop selecting foreign drivers 7. Revert "drm/mediatek: Switch to for_each_child_of_node_scoped()" 8. Fix YCbCr422 color format issue for DP 9. Fix mode valid issue for dp 10. dp: Reference common DAI properties 11. dsi: Add registers to pdata to fix MT8186/MT8188 12. Remove unneeded semicolon 13. Add return value check when reading DPCD 14. Initialize pointer in mtk_drm_of_ddp_path_build_one() Signed-off-by: Dave Airlie <airlied@redhat.com> From: Chun-Kuang Hu <chunkuang.hu@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20250104124227.45505-1-chunkuang.hu@kernel.org
This commit is contained in:
Dave Airlie
commit
fddb4fd91a
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@ -42,6 +42,9 @@ properties:
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interrupts:
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maxItems: 1
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'#sound-dai-cells':
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const: 0
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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@ -85,7 +88,21 @@ required:
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- ports
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- max-linkrate-mhz
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additionalProperties: false
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allOf:
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- $ref: /schemas/sound/dai-common.yaml#
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- if:
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not:
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properties:
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compatible:
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contains:
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enum:
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- mediatek,mt8188-dp-tx
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- mediatek,mt8195-dp-tx
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then:
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properties:
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'#sound-dai-cells': false
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unevaluatedProperties: false
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examples:
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- |
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@ -14,9 +14,6 @@ config DRM_MEDIATEK
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select DRM_BRIDGE_CONNECTOR
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select DRM_MIPI_DSI
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select DRM_PANEL
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select MEMORY
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select MTK_SMI
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select PHY_MTK_MIPI_DSI
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select VIDEOMODE_HELPERS
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help
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Choose this option if you have a Mediatek SoCs.
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@ -27,7 +24,6 @@ config DRM_MEDIATEK
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config DRM_MEDIATEK_DP
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tristate "DRM DPTX Support for MediaTek SoCs"
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depends on DRM_MEDIATEK
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select PHY_MTK_DP
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select DRM_DISPLAY_HELPER
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select DRM_DISPLAY_DP_HELPER
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select DRM_DISPLAY_DP_AUX_BUS
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@ -38,6 +34,5 @@ config DRM_MEDIATEK_HDMI
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tristate "DRM HDMI Support for Mediatek SoCs"
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depends on DRM_MEDIATEK
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select SND_SOC_HDMI_CODEC if SND_SOC
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select PHY_MTK_HDMI
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help
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DRM/KMS HDMI driver for Mediatek SoCs
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@ -112,6 +112,11 @@ static void mtk_drm_finish_page_flip(struct mtk_crtc *mtk_crtc)
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drm_crtc_handle_vblank(&mtk_crtc->base);
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#if IS_REACHABLE(CONFIG_MTK_CMDQ)
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if (mtk_crtc->cmdq_client.chan)
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return;
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#endif
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spin_lock_irqsave(&mtk_crtc->config_lock, flags);
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if (!mtk_crtc->config_updating && mtk_crtc->pending_needs_vblank) {
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mtk_crtc_finish_page_flip(mtk_crtc);
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@ -284,10 +289,8 @@ static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg)
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state = to_mtk_crtc_state(mtk_crtc->base.state);
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spin_lock_irqsave(&mtk_crtc->config_lock, flags);
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if (mtk_crtc->config_updating) {
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spin_unlock_irqrestore(&mtk_crtc->config_lock, flags);
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if (mtk_crtc->config_updating)
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goto ddp_cmdq_cb_out;
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}
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state->pending_config = false;
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@ -315,10 +318,15 @@ static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg)
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mtk_crtc->pending_async_planes = false;
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}
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spin_unlock_irqrestore(&mtk_crtc->config_lock, flags);
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ddp_cmdq_cb_out:
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if (mtk_crtc->pending_needs_vblank) {
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mtk_crtc_finish_page_flip(mtk_crtc);
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mtk_crtc->pending_needs_vblank = false;
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}
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spin_unlock_irqrestore(&mtk_crtc->config_lock, flags);
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mtk_crtc->cmdq_vblank_cnt = 0;
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wake_up(&mtk_crtc->cb_blocking_queue);
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}
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@ -606,13 +614,18 @@ static void mtk_crtc_update_config(struct mtk_crtc *mtk_crtc, bool needs_vblank)
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*/
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mtk_crtc->cmdq_vblank_cnt = 3;
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spin_lock_irqsave(&mtk_crtc->config_lock, flags);
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mtk_crtc->config_updating = false;
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spin_unlock_irqrestore(&mtk_crtc->config_lock, flags);
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mbox_send_message(mtk_crtc->cmdq_client.chan, cmdq_handle);
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mbox_client_txdone(mtk_crtc->cmdq_client.chan, 0);
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}
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#endif
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#else
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spin_lock_irqsave(&mtk_crtc->config_lock, flags);
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mtk_crtc->config_updating = false;
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spin_unlock_irqrestore(&mtk_crtc->config_lock, flags);
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#endif
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mutex_unlock(&mtk_crtc->hw_lock);
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}
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@ -460,6 +460,29 @@ static unsigned int mtk_ovl_fmt_convert(struct mtk_disp_ovl *ovl,
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}
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}
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static void mtk_ovl_afbc_layer_config(struct mtk_disp_ovl *ovl,
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unsigned int idx,
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struct mtk_plane_pending_state *pending,
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struct cmdq_pkt *cmdq_pkt)
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{
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unsigned int pitch_msb = pending->pitch >> 16;
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unsigned int hdr_pitch = pending->hdr_pitch;
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unsigned int hdr_addr = pending->hdr_addr;
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if (pending->modifier != DRM_FORMAT_MOD_LINEAR) {
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mtk_ddp_write_relaxed(cmdq_pkt, hdr_addr, &ovl->cmdq_reg, ovl->regs,
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DISP_REG_OVL_HDR_ADDR(ovl, idx));
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mtk_ddp_write_relaxed(cmdq_pkt,
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OVL_PITCH_MSB_2ND_SUBBUF | pitch_msb,
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&ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx));
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mtk_ddp_write_relaxed(cmdq_pkt, hdr_pitch, &ovl->cmdq_reg, ovl->regs,
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DISP_REG_OVL_HDR_PITCH(ovl, idx));
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} else {
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mtk_ddp_write_relaxed(cmdq_pkt, pitch_msb,
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&ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx));
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}
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}
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void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
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struct mtk_plane_state *state,
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struct cmdq_pkt *cmdq_pkt)
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@ -467,25 +490,14 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
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struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
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struct mtk_plane_pending_state *pending = &state->pending;
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unsigned int addr = pending->addr;
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unsigned int hdr_addr = pending->hdr_addr;
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unsigned int pitch = pending->pitch;
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unsigned int hdr_pitch = pending->hdr_pitch;
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unsigned int pitch_lsb = pending->pitch & GENMASK(15, 0);
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unsigned int fmt = pending->format;
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unsigned int rotation = pending->rotation;
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unsigned int offset = (pending->y << 16) | pending->x;
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unsigned int src_size = (pending->height << 16) | pending->width;
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unsigned int blend_mode = state->base.pixel_blend_mode;
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unsigned int ignore_pixel_alpha = 0;
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unsigned int con;
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bool is_afbc = pending->modifier != DRM_FORMAT_MOD_LINEAR;
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union overlay_pitch {
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struct split_pitch {
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u16 lsb;
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u16 msb;
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} split_pitch;
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u32 pitch;
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} overlay_pitch;
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overlay_pitch.pitch = pitch;
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if (!pending->enable) {
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mtk_ovl_layer_off(dev, idx, cmdq_pkt);
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@ -513,22 +525,30 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
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ignore_pixel_alpha = OVL_CONST_BLEND;
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}
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if (pending->rotation & DRM_MODE_REFLECT_Y) {
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/*
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* Treat rotate 180 as flip x + flip y, and XOR the original rotation value
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* to flip x + flip y to support both in the same time.
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*/
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if (rotation & DRM_MODE_ROTATE_180)
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rotation ^= DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
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if (rotation & DRM_MODE_REFLECT_Y) {
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con |= OVL_CON_VIRT_FLIP;
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addr += (pending->height - 1) * pending->pitch;
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}
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if (pending->rotation & DRM_MODE_REFLECT_X) {
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if (rotation & DRM_MODE_REFLECT_X) {
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con |= OVL_CON_HORZ_FLIP;
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addr += pending->pitch - 1;
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}
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if (ovl->data->supports_afbc)
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mtk_ovl_set_afbc(ovl, cmdq_pkt, idx, is_afbc);
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mtk_ovl_set_afbc(ovl, cmdq_pkt, idx,
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pending->modifier != DRM_FORMAT_MOD_LINEAR);
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mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs,
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DISP_REG_OVL_CON(idx));
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mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb | ignore_pixel_alpha,
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mtk_ddp_write_relaxed(cmdq_pkt, pitch_lsb | ignore_pixel_alpha,
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&ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH(idx));
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mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs,
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DISP_REG_OVL_SRC_SIZE(idx));
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@ -537,19 +557,8 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
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mtk_ddp_write_relaxed(cmdq_pkt, addr, &ovl->cmdq_reg, ovl->regs,
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DISP_REG_OVL_ADDR(ovl, idx));
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if (is_afbc) {
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mtk_ddp_write_relaxed(cmdq_pkt, hdr_addr, &ovl->cmdq_reg, ovl->regs,
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DISP_REG_OVL_HDR_ADDR(ovl, idx));
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mtk_ddp_write_relaxed(cmdq_pkt,
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OVL_PITCH_MSB_2ND_SUBBUF | overlay_pitch.split_pitch.msb,
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&ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx));
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mtk_ddp_write_relaxed(cmdq_pkt, hdr_pitch, &ovl->cmdq_reg, ovl->regs,
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DISP_REG_OVL_HDR_PITCH(ovl, idx));
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} else {
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mtk_ddp_write_relaxed(cmdq_pkt,
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overlay_pitch.split_pitch.msb,
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&ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx));
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}
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if (ovl->data->supports_afbc)
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mtk_ovl_afbc_layer_config(ovl, idx, pending, cmdq_pkt);
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mtk_ovl_set_bit_depth(dev, idx, fmt, cmdq_pkt);
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mtk_ovl_layer_on(dev, idx, cmdq_pkt);
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@ -543,18 +543,16 @@ static int mtk_dp_set_color_format(struct mtk_dp *mtk_dp,
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enum dp_pixelformat color_format)
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{
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u32 val;
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/* update MISC0 */
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mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3034,
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color_format << DP_TEST_COLOR_FORMAT_SHIFT,
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DP_TEST_COLOR_FORMAT_MASK);
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u32 misc0_color;
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switch (color_format) {
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case DP_PIXELFORMAT_YUV422:
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val = PIXEL_ENCODE_FORMAT_DP_ENC0_P0_YCBCR422;
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misc0_color = DP_COLOR_FORMAT_YCbCr422;
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break;
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case DP_PIXELFORMAT_RGB:
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val = PIXEL_ENCODE_FORMAT_DP_ENC0_P0_RGB;
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misc0_color = DP_COLOR_FORMAT_RGB;
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break;
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default:
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drm_warn(mtk_dp->drm_dev, "Unsupported color format: %d\n",
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@ -562,6 +560,11 @@ static int mtk_dp_set_color_format(struct mtk_dp *mtk_dp,
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return -EINVAL;
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}
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/* update MISC0 */
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mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3034,
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misc0_color,
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DP_TEST_COLOR_FORMAT_MASK);
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mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_303C,
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val, PIXEL_ENCODE_FORMAT_DP_ENC0_P0_MASK);
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return 0;
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||||
|
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@ -2100,7 +2103,6 @@ static enum drm_connector_status mtk_dp_bdg_detect(struct drm_bridge *bridge)
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struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);
|
||||
enum drm_connector_status ret = connector_status_disconnected;
|
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bool enabled = mtk_dp->enabled;
|
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u8 sink_count = 0;
|
||||
|
||||
if (!mtk_dp->train_info.cable_plugged_in)
|
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return ret;
|
||||
|
|
@ -2115,8 +2117,8 @@ static enum drm_connector_status mtk_dp_bdg_detect(struct drm_bridge *bridge)
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|||
* function, we just need to check the HPD connection to check
|
||||
* whether we connect to a sink device.
|
||||
*/
|
||||
drm_dp_dpcd_readb(&mtk_dp->aux, DP_SINK_COUNT, &sink_count);
|
||||
if (DP_GET_SINK_COUNT(sink_count))
|
||||
|
||||
if (drm_dp_read_sink_count(&mtk_dp->aux) > 0)
|
||||
ret = connector_status_connected;
|
||||
|
||||
if (!enabled)
|
||||
|
|
@ -2408,12 +2410,19 @@ mtk_dp_bridge_mode_valid(struct drm_bridge *bridge,
|
|||
{
|
||||
struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);
|
||||
u32 bpp = info->color_formats & DRM_COLOR_FORMAT_YCBCR422 ? 16 : 24;
|
||||
u32 rate = min_t(u32, drm_dp_max_link_rate(mtk_dp->rx_cap) *
|
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drm_dp_max_lane_count(mtk_dp->rx_cap),
|
||||
drm_dp_bw_code_to_link_rate(mtk_dp->max_linkrate) *
|
||||
mtk_dp->max_lanes);
|
||||
u32 lane_count_min = mtk_dp->train_info.lane_count;
|
||||
u32 rate = drm_dp_bw_code_to_link_rate(mtk_dp->train_info.link_rate) *
|
||||
lane_count_min;
|
||||
|
||||
if (rate < mode->clock * bpp / 8)
|
||||
/*
|
||||
*FEC overhead is approximately 2.4% from DP 1.4a spec 2.2.1.4.2.
|
||||
*The down-spread amplitude shall either be disabled (0.0%) or up
|
||||
*to 0.5% from 1.4a 3.5.2.6. Add up to approximately 3% total overhead.
|
||||
*
|
||||
*Because rate is already divided by 10,
|
||||
*mode->clock does not need to be multiplied by 10
|
||||
*/
|
||||
if ((rate * 97 / 100) < (mode->clock * bpp / 8))
|
||||
return MODE_CLOCK_HIGH;
|
||||
|
||||
return MODE_OK;
|
||||
|
|
@ -2454,10 +2463,9 @@ static u32 *mtk_dp_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
|
|||
struct drm_display_mode *mode = &crtc_state->adjusted_mode;
|
||||
struct drm_display_info *display_info =
|
||||
&conn_state->connector->display_info;
|
||||
u32 rate = min_t(u32, drm_dp_max_link_rate(mtk_dp->rx_cap) *
|
||||
drm_dp_max_lane_count(mtk_dp->rx_cap),
|
||||
drm_dp_bw_code_to_link_rate(mtk_dp->max_linkrate) *
|
||||
mtk_dp->max_lanes);
|
||||
u32 lane_count_min = mtk_dp->train_info.lane_count;
|
||||
u32 rate = drm_dp_bw_code_to_link_rate(mtk_dp->train_info.link_rate) *
|
||||
lane_count_min;
|
||||
|
||||
*num_input_fmts = 0;
|
||||
|
||||
|
|
@ -2466,8 +2474,8 @@ static u32 *mtk_dp_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
|
|||
* datarate of YUV422 and sink device supports YUV422, we output YUV422
|
||||
* format. Use this condition, we can support more resolution.
|
||||
*/
|
||||
if ((rate < (mode->clock * 24 / 8)) &&
|
||||
(rate > (mode->clock * 16 / 8)) &&
|
||||
if (((rate * 97 / 100) < (mode->clock * 24 / 8)) &&
|
||||
((rate * 97 / 100) > (mode->clock * 16 / 8)) &&
|
||||
(display_info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) {
|
||||
input_fmts = kcalloc(1, sizeof(*input_fmts), GFP_KERNEL);
|
||||
if (!input_fmts)
|
||||
|
|
|
|||
|
|
@ -373,11 +373,12 @@ static bool mtk_drm_get_all_drm_priv(struct device *dev)
|
|||
struct mtk_drm_private *temp_drm_priv;
|
||||
struct device_node *phandle = dev->parent->of_node;
|
||||
const struct of_device_id *of_id;
|
||||
struct device_node *node;
|
||||
struct device *drm_dev;
|
||||
unsigned int cnt = 0;
|
||||
int i, j;
|
||||
|
||||
for_each_child_of_node_scoped(phandle->parent, node) {
|
||||
for_each_child_of_node(phandle->parent, node) {
|
||||
struct platform_device *pdev;
|
||||
|
||||
of_id = of_match_node(mtk_drm_of_ids, node);
|
||||
|
|
@ -406,8 +407,10 @@ static bool mtk_drm_get_all_drm_priv(struct device *dev)
|
|||
if (temp_drm_priv->mtk_drm_bound)
|
||||
cnt++;
|
||||
|
||||
if (cnt == MAX_CRTC)
|
||||
if (cnt == MAX_CRTC) {
|
||||
of_node_put(node);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (drm_priv->data->mmsys_dev_num == cnt) {
|
||||
|
|
@ -673,6 +676,8 @@ static int mtk_drm_bind(struct device *dev)
|
|||
err_free:
|
||||
private->drm = NULL;
|
||||
drm_dev_put(drm);
|
||||
for (i = 0; i < private->data->mmsys_dev_num; i++)
|
||||
private->all_drm_private[i]->drm = NULL;
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -900,7 +905,7 @@ static int mtk_drm_of_ddp_path_build_one(struct device *dev, enum mtk_crtc_path
|
|||
const unsigned int **out_path,
|
||||
unsigned int *out_path_len)
|
||||
{
|
||||
struct device_node *next, *prev, *vdo = dev->parent->of_node;
|
||||
struct device_node *next = NULL, *prev, *vdo = dev->parent->of_node;
|
||||
unsigned int temp_path[DDP_COMPONENT_DRM_ID_MAX] = { 0 };
|
||||
unsigned int *final_ddp_path;
|
||||
unsigned short int idx = 0;
|
||||
|
|
@ -1089,7 +1094,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
|
|||
/* No devicetree graphs support: go with hardcoded paths if present */
|
||||
dev_dbg(dev, "Using hardcoded paths for MMSYS %u\n", mtk_drm_data->mmsys_id);
|
||||
private->data = mtk_drm_data;
|
||||
};
|
||||
}
|
||||
|
||||
private->all_drm_private = devm_kmalloc_array(dev, private->data->mmsys_dev_num,
|
||||
sizeof(*private->all_drm_private),
|
||||
|
|
|
|||
|
|
@ -139,11 +139,11 @@
|
|||
#define CLK_HS_POST GENMASK(15, 8)
|
||||
#define CLK_HS_EXIT GENMASK(23, 16)
|
||||
|
||||
#define DSI_VM_CMD_CON 0x130
|
||||
/* DSI_VM_CMD_CON */
|
||||
#define VM_CMD_EN BIT(0)
|
||||
#define TS_VFP_EN BIT(5)
|
||||
|
||||
#define DSI_SHADOW_DEBUG 0x190U
|
||||
/* DSI_SHADOW_DEBUG */
|
||||
#define FORCE_COMMIT BIT(0)
|
||||
#define BYPASS_SHADOW BIT(1)
|
||||
|
||||
|
|
@ -187,6 +187,8 @@ struct phy;
|
|||
|
||||
struct mtk_dsi_driver_data {
|
||||
const u32 reg_cmdq_off;
|
||||
const u32 reg_vm_cmd_off;
|
||||
const u32 reg_shadow_dbg_off;
|
||||
bool has_shadow_ctl;
|
||||
bool has_size_ctl;
|
||||
bool cmdq_long_packet_ctl;
|
||||
|
|
@ -246,23 +248,22 @@ static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
|
|||
u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, HZ_PER_MHZ);
|
||||
struct mtk_phy_timing *timing = &dsi->phy_timing;
|
||||
|
||||
timing->lpx = (80 * data_rate_mhz / (8 * 1000)) + 1;
|
||||
timing->da_hs_prepare = (59 * data_rate_mhz + 4 * 1000) / 8000 + 1;
|
||||
timing->da_hs_zero = (163 * data_rate_mhz + 11 * 1000) / 8000 + 1 -
|
||||
timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1;
|
||||
timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000;
|
||||
timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 -
|
||||
timing->da_hs_prepare;
|
||||
timing->da_hs_trail = (78 * data_rate_mhz + 7 * 1000) / 8000 + 1;
|
||||
timing->da_hs_trail = timing->da_hs_prepare + 1;
|
||||
|
||||
timing->ta_go = 4 * timing->lpx;
|
||||
timing->ta_sure = 3 * timing->lpx / 2;
|
||||
timing->ta_get = 5 * timing->lpx;
|
||||
timing->da_hs_exit = (118 * data_rate_mhz / (8 * 1000)) + 1;
|
||||
timing->ta_go = 4 * timing->lpx - 2;
|
||||
timing->ta_sure = timing->lpx + 2;
|
||||
timing->ta_get = 4 * timing->lpx;
|
||||
timing->da_hs_exit = 2 * timing->lpx + 1;
|
||||
|
||||
timing->clk_hs_prepare = (57 * data_rate_mhz / (8 * 1000)) + 1;
|
||||
timing->clk_hs_post = (65 * data_rate_mhz + 53 * 1000) / 8000 + 1;
|
||||
timing->clk_hs_trail = (78 * data_rate_mhz + 7 * 1000) / 8000 + 1;
|
||||
timing->clk_hs_zero = (330 * data_rate_mhz / (8 * 1000)) + 1 -
|
||||
timing->clk_hs_prepare;
|
||||
timing->clk_hs_exit = (118 * data_rate_mhz / (8 * 1000)) + 1;
|
||||
timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000);
|
||||
timing->clk_hs_post = timing->clk_hs_prepare + 8;
|
||||
timing->clk_hs_trail = timing->clk_hs_prepare;
|
||||
timing->clk_hs_zero = timing->clk_hs_trail * 4;
|
||||
timing->clk_hs_exit = 2 * timing->clk_hs_trail;
|
||||
|
||||
timcon0 = FIELD_PREP(LPX, timing->lpx) |
|
||||
FIELD_PREP(HS_PREP, timing->da_hs_prepare) |
|
||||
|
|
@ -367,8 +368,8 @@ static void mtk_dsi_set_mode(struct mtk_dsi *dsi)
|
|||
|
||||
static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi)
|
||||
{
|
||||
mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN);
|
||||
mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN);
|
||||
mtk_dsi_mask(dsi, dsi->driver_data->reg_vm_cmd_off, VM_CMD_EN, VM_CMD_EN);
|
||||
mtk_dsi_mask(dsi, dsi->driver_data->reg_vm_cmd_off, TS_VFP_EN, TS_VFP_EN);
|
||||
}
|
||||
|
||||
static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi)
|
||||
|
|
@ -714,7 +715,7 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
|
|||
|
||||
if (dsi->driver_data->has_shadow_ctl)
|
||||
writel(FORCE_COMMIT | BYPASS_SHADOW,
|
||||
dsi->regs + DSI_SHADOW_DEBUG);
|
||||
dsi->regs + dsi->driver_data->reg_shadow_dbg_off);
|
||||
|
||||
mtk_dsi_reset_engine(dsi);
|
||||
mtk_dsi_phy_timconfig(dsi);
|
||||
|
|
@ -1263,26 +1264,36 @@ static void mtk_dsi_remove(struct platform_device *pdev)
|
|||
|
||||
static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = {
|
||||
.reg_cmdq_off = 0x200,
|
||||
.reg_vm_cmd_off = 0x130,
|
||||
.reg_shadow_dbg_off = 0x190
|
||||
};
|
||||
|
||||
static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = {
|
||||
.reg_cmdq_off = 0x180,
|
||||
.reg_vm_cmd_off = 0x130,
|
||||
.reg_shadow_dbg_off = 0x190
|
||||
};
|
||||
|
||||
static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = {
|
||||
.reg_cmdq_off = 0x200,
|
||||
.reg_vm_cmd_off = 0x130,
|
||||
.reg_shadow_dbg_off = 0x190,
|
||||
.has_shadow_ctl = true,
|
||||
.has_size_ctl = true,
|
||||
};
|
||||
|
||||
static const struct mtk_dsi_driver_data mt8186_dsi_driver_data = {
|
||||
.reg_cmdq_off = 0xd00,
|
||||
.reg_vm_cmd_off = 0x200,
|
||||
.reg_shadow_dbg_off = 0xc00,
|
||||
.has_shadow_ctl = true,
|
||||
.has_size_ctl = true,
|
||||
};
|
||||
|
||||
static const struct mtk_dsi_driver_data mt8188_dsi_driver_data = {
|
||||
.reg_cmdq_off = 0xd00,
|
||||
.reg_vm_cmd_off = 0x200,
|
||||
.reg_shadow_dbg_off = 0xc00,
|
||||
.has_shadow_ctl = true,
|
||||
.has_size_ctl = true,
|
||||
.cmdq_long_packet_ctl = true,
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user