mirror of
https://github.com/torvalds/linux.git
synced 2026-11-07 06:17:02 +01:00
Renesas DTS updates for v7.4 (take two)
- Add PCIe support for the RZ/G3L SoC,
- Add ADC DMA support for the RZ/T2H and RZ/N2H SoCs,
- Add initial support for the RZ/G2M v3.0 SoC and the HopeRun HiHope
RZ/G2M v3.0 board stack,
- Add USB support for the RZ/G3E SoC and the RZ/G3E SMARC EVK board,
- Add SPI (MSIOF) and I2C support for the R-Car X5H SoC,
- Add support for various SolidRun boards based on RZ/G2L, RZ/G2LC,
RZ/V2L, and RZ/G2UL,
- Miscellaneous fixes and improvements.
-----BEGIN PGP SIGNATURE-----
iHUEABYKAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCar+QkQAKCRCKwlD9ZEnx
cAURAP9LsgtbmGOsZDPjSos93kek1u68o6aJoMUZl2f4jMi0FgEA7DKw2djB3c8F
wWyvlOTcAJx/J3Zk7dKcuYc+Nkem+wA=
=htI+
-----END PGP SIGNATURE-----
Merge tag 'renesas-dts-for-v7.4-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v7.4 (take two)
- Add PCIe support for the RZ/G3L SoC,
- Add ADC DMA support for the RZ/T2H and RZ/N2H SoCs,
- Add initial support for the RZ/G2M v3.0 SoC and the HopeRun HiHope
RZ/G2M v3.0 board stack,
- Add USB support for the RZ/G3E SoC and the RZ/G3E SMARC EVK board,
- Add SPI (MSIOF) and I2C support for the R-Car X5H SoC,
- Add support for various SolidRun boards based on RZ/G2L, RZ/G2LC,
RZ/V2L, and RZ/G2UL,
- Miscellaneous fixes and improvements.
* tag 'renesas-dts-for-v7.4-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (34 commits)
arm64: dts: renesas: Add support for solidrun rzg2ul som on hb-ripple
arm64: dts: renesas: Add support for solidrun hb-ripple with rzg2lc som
arm64: dts: renesas: Add support for solidrun hb-ripple with rzv2l som
arm64: dts: renesas: Add support for solidrun hb-ripple with rzg2l som
arm64: dts: renesas: rzg2l(c)/rzv2l hb-iiot: Add dsi panel dt overlay
arm64: dts: renesas: Add support for solidrun rzg2lc som and hb-iiot evb
arm64: dts: renesas: Add support for solidrun rzv2l som and hb-iiot evb
arm64: dts: renesas: Add support for solidrun rzg2l som and hb-iiot evb
dt-bindings: soc: renesas: Add various SolidRun RZ/G2 based boards
arm64: dts: renesas: r8a779h0: Add PCIe Application/Local register reset
arm64: dts: renesas: r8a779g0: Add PCIe Application/Local register reset
arm64: dts: renesas: r8a779f0: Add PCIe Application/Local register reset
arm64: dts: renesas: r8a78000: Add I2C nodes
arm64: dts: renesas: r8a78000: Add MSIOF nodes
dt-bindings: clock: renesas,r8a78000-cpg: Add MSIOF clocks
arm64: dts: renesas: r9a09g047e57-smarc: Enable USB2.0 support
arm64: dts: renesas: r9a09g047: Add USB2.0 support
arm64: dts: renesas: r9a08g046: Add USB2.0 placeholder nodes
arm64: dts: renesas: Add HiHope RZ/G2M v3.0 SoC sub board support
arm64: dts: renesas: Add HiHope RZ/G2M v3.0 SoC main board support
...
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
This commit is contained in:
Alexandre Belloni
commit
fd4bcf8d28
|
|
@ -21,6 +21,7 @@ properties:
|
|||
- qcom,glymur-rpmhpd
|
||||
- qcom,hawi-rpmhpd
|
||||
- qcom,kaanapali-rpmhpd
|
||||
- qcom,kuno-rpmhpd
|
||||
- qcom,mdm9607-rpmpd
|
||||
- qcom,milos-rpmhpd
|
||||
- qcom,msm8226-rpmpd
|
||||
|
|
@ -63,6 +64,7 @@ properties:
|
|||
- qcom,sm6350-rpmhpd
|
||||
- qcom,sm6375-rpmpd
|
||||
- qcom,sm7150-rpmhpd
|
||||
- qcom,sm7250-rpmhpd
|
||||
- qcom,sm8150-rpmhpd
|
||||
- qcom,sm8250-rpmhpd
|
||||
- qcom,sm8350-rpmhpd
|
||||
|
|
|
|||
|
|
@ -13,8 +13,11 @@ maintainers:
|
|||
description: |
|
||||
The R-Car (RZ/G) System Controller provides power management for the CPU
|
||||
cores and various coprocessors.
|
||||
The power domain IDs for consumers are defined in header files:
|
||||
include/dt-bindings/power/r8*-sysc.h
|
||||
The power domain IDs for consumers are defined in the below header files
|
||||
(where the asterisk serves as a wildcard matching the specific SoC
|
||||
identifier):
|
||||
include/dt-bindings/power/r8*-sysc.h or
|
||||
include/dt-bindings/power/renesas,r8*-sysc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,65 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/power/riscv,rpmi-device-power.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: RISC-V RPMI device power service group based power domain controller
|
||||
|
||||
maintainers:
|
||||
- Joshua Yeong <joshua.yeong@starfivetech.com>
|
||||
|
||||
description: |
|
||||
The RISC-V Platform Management Interface (RPMI) [1] defines a
|
||||
messaging protocol which is modular and extensible. The supervisor
|
||||
software can send/receive RPMI messages via SBI MPXY extension [2]
|
||||
or some dedicated supervisor-mode RPMI transport.
|
||||
|
||||
The RPMI specification [1] defines device power service group for
|
||||
accessing and controlling the power state of platform devices managed
|
||||
by a platform microcontroller. The supervisor software can access RPMI
|
||||
device power service group via SBI MPXY channel or some dedicated
|
||||
supervisor-mode RPMI transport.
|
||||
|
||||
===========================================
|
||||
References
|
||||
===========================================
|
||||
|
||||
[1] RISC-V Platform Management Interface (RPMI) v1.0 (or higher)
|
||||
https://github.com/riscv-non-isa/riscv-rpmi/releases
|
||||
|
||||
[2] RISC-V Supervisor Binary Interface (SBI) v3.0 (or higher)
|
||||
https://github.com/riscv-non-isa/riscv-sbi-doc/releases
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
description:
|
||||
Intended for use by the supervisor software.
|
||||
const: riscv,rpmi-device-power
|
||||
|
||||
mboxes:
|
||||
maxItems: 1
|
||||
description:
|
||||
Mailbox channel of the underlying RPMI transport or SBI message proxy channel.
|
||||
|
||||
"#power-domain-cells":
|
||||
const: 1
|
||||
description:
|
||||
Platform specific DOMAIN_ID as defined by the RISC-V Platform Management
|
||||
Interface (RPMI) specification.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- mboxes
|
||||
- "#power-domain-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
power-controller {
|
||||
compatible = "riscv,rpmi-device-power";
|
||||
mboxes = <&mpxy_mbox 0x1002 0x0>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/power/riscv,rpmi-mpxy-device-power.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: RISC-V RPMI device power service group based message proxy
|
||||
|
||||
maintainers:
|
||||
- Joshua Yeong <joshua.yeong@starfivetech.com>
|
||||
|
||||
description: |
|
||||
The RISC-V Platform Management Interface (RPMI) [1] defines a
|
||||
messaging protocol which is modular and extensible. The supervisor
|
||||
software can send/receive RPMI messages via SBI MPXY extension [2]
|
||||
or some dedicated supervisor-mode RPMI transport.
|
||||
|
||||
The RPMI specification [1] defines device power service group for
|
||||
accessing and controlling the power state of platform devices managed
|
||||
by a platform microcontroller. The SBI implementation (machine mode
|
||||
firmware or hypervisor) can implement an SBI MPXY channel to allow RPMI
|
||||
device power service group access to the supervisor software.
|
||||
|
||||
===========================================
|
||||
References
|
||||
===========================================
|
||||
|
||||
[1] RISC-V Platform Management Interface (RPMI) v1.0 (or higher)
|
||||
https://github.com/riscv-non-isa/riscv-rpmi/releases
|
||||
|
||||
[2] RISC-V Supervisor Binary Interface (SBI) v3.0 (or higher)
|
||||
https://github.com/riscv-non-isa/riscv-sbi-doc/releases
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
description:
|
||||
Intended for use by the SBI implementation.
|
||||
const: riscv,rpmi-mpxy-device-power
|
||||
|
||||
mboxes:
|
||||
maxItems: 1
|
||||
description:
|
||||
Mailbox channel of the underlying RPMI transport.
|
||||
|
||||
riscv,sbi-mpxy-channel-id:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
The SBI MPXY channel id to be used for providing RPMI access to
|
||||
the supervisor software.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- mboxes
|
||||
- riscv,sbi-mpxy-channel-id
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
device-power-service {
|
||||
compatible = "riscv,rpmi-mpxy-device-power";
|
||||
mboxes = <&rpmi_shmem_mbox 0x9>;
|
||||
riscv,sbi-mpxy-channel-id = <0x1002>;
|
||||
};
|
||||
...
|
||||
|
|
@ -508,6 +508,14 @@ properties:
|
|||
- renesas,r9a07g043u12 # RZ/G2UL Type-2
|
||||
- const: renesas,r9a07g043
|
||||
|
||||
- description: SolidRun RZ/G2UL based boards
|
||||
items:
|
||||
- enum:
|
||||
- solidrun,rzg2ul-hummingboard-ripple # SolidRun RZ/G2UL HummingBoard Ripple
|
||||
- const: solidrun,rzg2ul-sr-som
|
||||
- const: renesas,r9a07g043u12 # RZ/G2UL Type-2
|
||||
- const: renesas,r9a07g043
|
||||
|
||||
- description: RZ/G2{L,LC} (R9A07G044)
|
||||
items:
|
||||
- enum:
|
||||
|
|
@ -519,6 +527,25 @@ properties:
|
|||
- renesas,r9a07g044l2 # Dual Cortex-A55 RZ/G2L
|
||||
- const: renesas,r9a07g044
|
||||
|
||||
- description: SolidRun RZ/G2L based boards
|
||||
items:
|
||||
- enum:
|
||||
- solidrun,rzg2l-hummingboard-iiot # SolidRun RZ/G2L HummingBoard IIoT
|
||||
- solidrun,rzg2l-hummingboard-pro # SolidRun RZ/G2L HummingBoard Pro
|
||||
- solidrun,rzg2l-hummingboard-ripple # SolidRun RZ/G2L HummingBoard Ripple
|
||||
- const: solidrun,rzg2l-sr-som
|
||||
- const: renesas,r9a07g044l2 # Dual Cortex-A55 RZ/G2L
|
||||
- const: renesas,r9a07g044
|
||||
|
||||
- description: SolidRun RZ/G2LC based boards
|
||||
items:
|
||||
- enum:
|
||||
- solidrun,rzg2lc-hummingboard-iiot # SolidRun RZ/G2LC HummingBoard IIoT
|
||||
- solidrun,rzg2lc-hummingboard-ripple # SolidRun RZ/G2LC HummingBoard Ripple
|
||||
- const: solidrun,rzg2lc-sr-som
|
||||
- const: renesas,r9a07g044c2 # Dual Cortex-A55 RZ/G2LC
|
||||
- const: renesas,r9a07g044
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
# MYIR Remi Pi SBC (MYB-YG2LX-REMI)
|
||||
|
|
@ -535,6 +562,16 @@ properties:
|
|||
- renesas,r9a07g054l2 # Dual Cortex-A55 RZ/V2L
|
||||
- const: renesas,r9a07g054
|
||||
|
||||
- description: SolidRun RZ/V2L based boards
|
||||
items:
|
||||
- enum:
|
||||
- solidrun,rzv2l-hummingboard-iiot # SolidRun RZ/V2L HummingBoard IIoT
|
||||
- solidrun,rzv2l-hummingboard-pro # SolidRun RZ/V2L HummingBoard Pro
|
||||
- solidrun,rzv2l-hummingboard-ripple # SolidRun RZ/V2L HummingBoard Ripple
|
||||
- const: solidrun,rzv2l-sr-som
|
||||
- const: renesas,r9a07g054l2 # Dual Cortex-A55 RZ/V2L
|
||||
- const: renesas,r9a07g054
|
||||
|
||||
- description: RZ/G3S (R9A08G045)
|
||||
items:
|
||||
- enum:
|
||||
|
|
|
|||
|
|
@ -8,6 +8,9 @@ dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2.dtb
|
|||
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex.dtb
|
||||
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_R8A774A3) += r8a774a3-hihope-rzg2m.dtb
|
||||
dtb-$(CONFIG_ARCH_R8A774A3) += r8a774a3-hihope-rzg2m-ex.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-beacon-rzg2n-kit.dtb
|
||||
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n.dtb
|
||||
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex.dtb
|
||||
|
|
@ -167,18 +170,89 @@ r9a07g043u11-smarc-du-adv7513-dtbs := r9a07g043u11-smarc.dtb r9a07g043u11-smarc-
|
|||
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-du-adv7513.dtb
|
||||
r9a07g043u11-smarc-pmod-dtbs := r9a07g043u11-smarc.dtb r9a07g043-smarc-pmod.dtbo
|
||||
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-pmod.dtb
|
||||
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u12-hummingboard-ripple.dtb
|
||||
dtb-$(CONFIG_ARCH_R9A07G043) += rzg2l-sr-som-emmc.dtbo
|
||||
r9a07g043u12-hummingboard-ripple-emmc-dtbs := r9a07g043u12-hummingboard-ripple.dtb rzg2l-sr-som-emmc.dtbo
|
||||
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u12-hummingboard-ripple-emmc.dtb
|
||||
dtb-$(CONFIG_ARCH_R9A07G043) += rzg2l-hummingboard-iiot-microsd.dtbo
|
||||
dtb-$(CONFIG_ARCH_R9A07G043) += rzg2ul-hummingboard-pulse-leds.dtbo
|
||||
r9a07g043u12-hummingboard-ripple-leds-dtbs := r9a07g043u12-hummingboard-ripple.dtb rzg2ul-hummingboard-pulse-leds.dtbo
|
||||
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u12-hummingboard-ripple-leds.dtb
|
||||
r9a07g043u12-hummingboard-ripple-microsd-dtbs := r9a07g043u12-hummingboard-ripple.dtb rzg2l-hummingboard-iiot-microsd.dtbo
|
||||
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u12-hummingboard-ripple-microsd.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot.dtb
|
||||
r9a07g044c2-hummingboard-iiot-emmc-dtbs := r9a07g044c2-hummingboard-iiot.dtb rzg2l-sr-som-emmc.dtbo
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-emmc.dtb
|
||||
r9a07g044c2-hummingboard-iiot-microsd-dtbs := r9a07g044c2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-microsd.dtbo
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-microsd.dtb
|
||||
r9a07g044c2-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0-dtbs := r9a07g044c2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtbo
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtb
|
||||
r9a07g044c2-hummingboard-iiot-rs485-a-dtbs := r9a07g044c2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-a.dtbo
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-rs485-a.dtb
|
||||
r9a07g044c2-hummingboard-iiot-rs485-b-dtbs := r9a07g044c2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-b.dtbo
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-iiot-rs485-b.dtb
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-ripple.dtb
|
||||
r9a07g044c2-hummingboard-ripple-emmc-dtbs := r9a07g044c2-hummingboard-ripple.dtb rzg2l-sr-som-emmc.dtbo
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-ripple-emmc.dtb
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += rzg2lc-hummingboard-pulse-leds.dtbo
|
||||
r9a07g044c2-hummingboard-ripple-leds-dtbs := r9a07g044c2-hummingboard-ripple.dtb rzg2lc-hummingboard-pulse-leds.dtbo
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-ripple-leds.dtb
|
||||
r9a07g044c2-hummingboard-ripple-microsd-dtbs := r9a07g044c2-hummingboard-ripple.dtb rzg2l-hummingboard-iiot-microsd.dtbo
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-hummingboard-ripple-microsd.dtb
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtbo
|
||||
r9a07g044c2-smarc-cru-csi-ov5645-dtbs := r9a07g044c2-smarc.dtb r9a07g044c2-smarc-cru-csi-ov5645.dtbo
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot.dtb
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-sr-som-emmc.dtbo
|
||||
r9a07g044l2-hummingboard-iiot-emmc-dtbs := r9a07g044l2-hummingboard-iiot.dtb rzg2l-sr-som-emmc.dtbo
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot-emmc.dtb
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-hummingboard-iiot-microsd.dtbo
|
||||
r9a07g044l2-hummingboard-iiot-microsd-dtbs := r9a07g044l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-microsd.dtbo
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot-microsd.dtb
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtbo
|
||||
r9a07g044l2-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0-dtbs := r9a07g044l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtbo
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtb
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-hummingboard-iiot-rs485-a.dtbo
|
||||
r9a07g044l2-hummingboard-iiot-rs485-a-dtbs := r9a07g044l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-a.dtbo
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot-rs485-a.dtb
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += rzg2l-hummingboard-iiot-rs485-b.dtbo
|
||||
r9a07g044l2-hummingboard-iiot-rs485-b-dtbs := r9a07g044l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-b.dtbo
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-iiot-rs485-b.dtb
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-ripple.dtb
|
||||
r9a07g044l2-hummingboard-ripple-emmc-dtbs := r9a07g044l2-hummingboard-ripple.dtb rzg2l-sr-som-emmc.dtbo
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-ripple-emmc.dtb
|
||||
r9a07g044l2-hummingboard-ripple-microsd-dtbs := r9a07g044l2-hummingboard-ripple.dtb rzg2l-hummingboard-iiot-microsd.dtbo
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-hummingboard-ripple-microsd.dtb
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-remi-pi.dtb
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtbo
|
||||
r9a07g044l2-smarc-cru-csi-ov5645-dtbs := r9a07g044l2-smarc.dtb r9a07g044l2-smarc-cru-csi-ov5645.dtbo
|
||||
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-iiot.dtb
|
||||
dtb-$(CONFIG_ARCH_R9A07G054) += rzg2l-sr-som-emmc.dtbo
|
||||
r9a07g054l2-hummingboard-iiot-emmc-dtbs := r9a07g054l2-hummingboard-iiot.dtb rzg2l-sr-som-emmc.dtbo
|
||||
dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-iiot-emmc.dtb
|
||||
dtb-$(CONFIG_ARCH_R9A07G054) += rzg2l-hummingboard-iiot-microsd.dtbo
|
||||
r9a07g054l2-hummingboard-iiot-microsd-dtbs := r9a07g054l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-microsd.dtbo
|
||||
dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-iiot-microsd.dtb
|
||||
dtb-$(CONFIG_ARCH_R9A07G054) += rzg2l-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtbo
|
||||
r9a07g054l2-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0-dtbs := r9a07g054l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtbo
|
||||
dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtb
|
||||
dtb-$(CONFIG_ARCH_R9A07G054) += rzg2l-hummingboard-iiot-rs485-a.dtbo
|
||||
r9a07g054l2-hummingboard-iiot-rs485-a-dtbs := r9a07g054l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-a.dtbo
|
||||
dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-iiot-rs485-a.dtb
|
||||
dtb-$(CONFIG_ARCH_R9A07G054) += rzg2l-hummingboard-iiot-rs485-b.dtbo
|
||||
r9a07g054l2-hummingboard-iiot-rs485-b-dtbs := r9a07g054l2-hummingboard-iiot.dtb rzg2l-hummingboard-iiot-rs485-b.dtbo
|
||||
dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-iiot-rs485-b.dtb
|
||||
dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-ripple.dtb
|
||||
r9a07g054l2-hummingboard-ripple-emmc-dtbs := r9a07g054l2-hummingboard-ripple.dtb rzg2l-sr-som-emmc.dtbo
|
||||
dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-ripple-emmc.dtb
|
||||
r9a07g054l2-hummingboard-ripple-microsd-dtbs := r9a07g054l2-hummingboard-ripple.dtb rzg2l-hummingboard-iiot-microsd.dtbo
|
||||
dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-hummingboard-ripple-microsd.dtb
|
||||
dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb
|
||||
dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc-cru-csi-ov5645.dtbo
|
||||
r9a07g054l2-smarc-cru-csi-ov5645-dtbs := r9a07g054l2-smarc.dtb r9a07g054l2-smarc-cru-csi-ov5645.dtbo
|
||||
|
|
|
|||
14
arch/arm64/boot/dts/renesas/r8a774a3-hihope-rzg2m-ex.dts
Normal file
14
arch/arm64/boot/dts/renesas/r8a774a3-hihope-rzg2m-ex.dts
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
/*
|
||||
* Device Tree Source for the HiHope RZ/G2M v3.0 SoC sub board
|
||||
*
|
||||
* Copyright (C) 2026 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include "r8a774a3-hihope-rzg2m.dts"
|
||||
|
||||
/ {
|
||||
model = "HopeRun HiHope RZ/G2M v3.0 with sub board";
|
||||
compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2m",
|
||||
"renesas,r8a774a3";
|
||||
};
|
||||
49
arch/arm64/boot/dts/renesas/r8a774a3-hihope-rzg2m.dts
Normal file
49
arch/arm64/boot/dts/renesas/r8a774a3-hihope-rzg2m.dts
Normal file
|
|
@ -0,0 +1,49 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
/*
|
||||
* Device Tree Source for the HiHope RZ/G2M v3.0 SoC main board
|
||||
*
|
||||
* Copyright (C) 2026 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a774a3.dtsi"
|
||||
|
||||
/ {
|
||||
model = "HopeRun HiHope RZ/G2M v3.0 main board based on r8a774a3";
|
||||
compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a3";
|
||||
|
||||
memory@48000000 {
|
||||
device_type = "memory";
|
||||
/* First 128MiB is reserved for secure area */
|
||||
reg = <0x0 0x48000000 0x0 0x78000000>;
|
||||
};
|
||||
|
||||
memory@600000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x6 0x00000000 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &scif2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <16666666>;
|
||||
};
|
||||
|
||||
&extalr_clk {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
&scif2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif_clk {
|
||||
clock-frequency = <14745600>;
|
||||
};
|
||||
302
arch/arm64/boot/dts/renesas/r8a774a3.dtsi
Normal file
302
arch/arm64/boot/dts/renesas/r8a774a3.dtsi
Normal file
|
|
@ -0,0 +1,302 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
/*
|
||||
* Device Tree Source for the r8a774a3 SoC
|
||||
*
|
||||
* Copyright (C) 2026 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/renesas,r8a774a3-cpg-mssr.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/renesas,r8a774a3-sysc.h>
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a774a3";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
cluster0_opp: opp-table-0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-500000000 {
|
||||
opp-hz = /bits/ 64 <500000000>;
|
||||
opp-microvolt = <820000>;
|
||||
clock-latency-ns = <300000>;
|
||||
};
|
||||
opp-1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
opp-microvolt = <820000>;
|
||||
clock-latency-ns = <300000>;
|
||||
};
|
||||
opp-1500000000 {
|
||||
opp-hz = /bits/ 64 <1500000000>;
|
||||
opp-microvolt = <820000>;
|
||||
clock-latency-ns = <300000>;
|
||||
opp-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1_opp: opp-table-1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-800000000 {
|
||||
opp-hz = /bits/ 64 <800000000>;
|
||||
opp-microvolt = <820000>;
|
||||
clock-latency-ns = <300000>;
|
||||
};
|
||||
opp-1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
opp-microvolt = <820000>;
|
||||
clock-latency-ns = <300000>;
|
||||
};
|
||||
opp-1200000000 {
|
||||
opp-hz = /bits/ 64 <1200000000>;
|
||||
opp-microvolt = <820000>;
|
||||
clock-latency-ns = <300000>;
|
||||
};
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&a57_0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&a57_1>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&a53_0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&a53_1>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&a53_2>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&a53_3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
a57_0: cpu@0 {
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A774A3_PD_CA57_CPU0>;
|
||||
next-level-cache = <&L2_CA57>;
|
||||
enable-method = "psci";
|
||||
dynamic-power-coefficient = <854>;
|
||||
clocks = <&cpg CPG_CORE R8A774A3_CLK_Z>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
};
|
||||
|
||||
a57_1: cpu@1 {
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A774A3_PD_CA57_CPU1>;
|
||||
next-level-cache = <&L2_CA57>;
|
||||
enable-method = "psci";
|
||||
clocks = <&cpg CPG_CORE R8A774A3_CLK_Z>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
};
|
||||
|
||||
a53_0: cpu@100 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x100>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A774A3_PD_CA53_CPU0>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
dynamic-power-coefficient = <277>;
|
||||
clocks = <&cpg CPG_CORE R8A774A3_CLK_Z2>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
capacity-dmips-mhz = <560>;
|
||||
};
|
||||
|
||||
a53_1: cpu@101 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x101>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A774A3_PD_CA53_CPU1>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
clocks = <&cpg CPG_CORE R8A774A3_CLK_Z2>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
capacity-dmips-mhz = <560>;
|
||||
};
|
||||
|
||||
a53_2: cpu@102 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x102>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A774A3_PD_CA53_CPU2>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
clocks = <&cpg CPG_CORE R8A774A3_CLK_Z2>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
capacity-dmips-mhz = <560>;
|
||||
};
|
||||
|
||||
a53_3: cpu@103 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x103>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A774A3_PD_CA53_CPU3>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
clocks = <&cpg CPG_CORE R8A774A3_CLK_Z2>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
capacity-dmips-mhz = <560>;
|
||||
};
|
||||
|
||||
L2_CA57: cache-controller-0 {
|
||||
compatible = "cache";
|
||||
power-domains = <&sysc R8A774A3_PD_CA57_SCU>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
L2_CA53: cache-controller-1 {
|
||||
compatible = "cache";
|
||||
power-domains = <&sysc R8A774A3_PD_CA53_SCU>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
extal_clk: extal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
extalr_clk: extalr {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
pmu-a53 {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
|
||||
};
|
||||
|
||||
pmu-a57 {
|
||||
compatible = "arm,cortex-a57-pmu";
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&a57_0>, <&a57_1>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0", "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
/* External SCIF clock - to be overridden by boards that provide it */
|
||||
scif_clk: scif {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
compatible = "simple-bus";
|
||||
bootph-all;
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
cpg: clock-controller@e6150000 {
|
||||
compatible = "renesas,r8a774a3-cpg-mssr";
|
||||
reg = <0 0xe6150000 0 0x1000>;
|
||||
clocks = <&extal_clk>, <&extalr_clk>;
|
||||
clock-names = "extal", "extalr";
|
||||
#clock-cells = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
rst: reset-controller@e6160000 {
|
||||
compatible = "renesas,r8a774a3-rst";
|
||||
reg = <0 0xe6160000 0 0x200>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
sysc: system-controller@e6180000 {
|
||||
compatible = "renesas,r8a774a3-sysc";
|
||||
reg = <0 0xe6180000 0 0x400>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
scif2: serial@e6e88000 {
|
||||
compatible = "renesas,scif-r8a774a3",
|
||||
"renesas,rcar-gen3-scif", "renesas,scif";
|
||||
reg = <0 0xe6e88000 0 0x40>;
|
||||
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 310>,
|
||||
<&cpg CPG_CORE R8A774A3_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
power-domains = <&sysc R8A774A3_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 310>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f1010000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0xf1010000 0 0x1000>,
|
||||
<0x0 0xf1020000 0 0x20000>,
|
||||
<0x0 0xf1040000 0 0x20000>,
|
||||
<0x0 0xf1060000 0 0x20000>;
|
||||
interrupts = <GIC_PPI 9
|
||||
(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&cpg CPG_MOD 408>;
|
||||
clock-names = "clk";
|
||||
power-domains = <&sysc R8A774A3_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 408>;
|
||||
};
|
||||
|
||||
prr: chipid@fff00044 {
|
||||
compatible = "renesas,prr";
|
||||
reg = <0 0xfff00044 0 4>;
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
|
||||
};
|
||||
};
|
||||
|
|
@ -790,8 +790,8 @@ pciec0: pcie@e65d0000 {
|
|||
clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
|
||||
clock-names = "core", "ref";
|
||||
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 624>;
|
||||
reset-names = "pwr";
|
||||
resets = <&cpg 624>, <&cpg 1121>;
|
||||
reset-names = "pwr", "core";
|
||||
max-link-speed = <4>;
|
||||
msi-parent = <&its 0>;
|
||||
msi-map = <0x0 &its 0x0 0x10000>;
|
||||
|
|
@ -829,8 +829,8 @@ pciec1: pcie@e65d8000 {
|
|||
clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>;
|
||||
clock-names = "core", "ref";
|
||||
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 625>;
|
||||
reset-names = "pwr";
|
||||
resets = <&cpg 625>, <&cpg 1122>;
|
||||
reset-names = "pwr", "core";
|
||||
max-link-speed = <4>;
|
||||
msi-parent = <&its 0>;
|
||||
msi-map = <0x0 &its 0x0 0x10000>;
|
||||
|
|
@ -867,8 +867,8 @@ pciec0_ep: pcie-ep@e65d0000 {
|
|||
clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
|
||||
clock-names = "core", "ref";
|
||||
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 624>;
|
||||
reset-names = "pwr";
|
||||
resets = <&cpg 624>, <&cpg 1121>;
|
||||
reset-names = "pwr", "core";
|
||||
max-link-speed = <4>;
|
||||
num-lanes = <2>;
|
||||
max-functions = /bits/ 8 <2>;
|
||||
|
|
@ -890,8 +890,8 @@ pciec1_ep: pcie-ep@e65d8000 {
|
|||
clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>;
|
||||
clock-names = "core", "ref";
|
||||
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 625>;
|
||||
reset-names = "pwr";
|
||||
resets = <&cpg 625>, <&cpg 1122>;
|
||||
reset-names = "pwr", "core";
|
||||
max-link-speed = <4>;
|
||||
num-lanes = <2>;
|
||||
max-functions = /bits/ 8 <2>;
|
||||
|
|
|
|||
|
|
@ -806,8 +806,8 @@ pciec0: pcie@e65d0000 {
|
|||
clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
|
||||
clock-names = "core", "ref";
|
||||
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 624>;
|
||||
reset-names = "pwr";
|
||||
resets = <&cpg 624>, <&cpg 1121>;
|
||||
reset-names = "pwr", "core";
|
||||
max-link-speed = <4>;
|
||||
msi-parent = <&its 0>;
|
||||
msi-map = <0x0 &its 0x0 0x10000>;
|
||||
|
|
@ -855,8 +855,8 @@ pciec1: pcie@e65d8000 {
|
|||
clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>;
|
||||
clock-names = "core", "ref";
|
||||
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 625>;
|
||||
reset-names = "pwr";
|
||||
resets = <&cpg 625>, <&cpg 1122>;
|
||||
reset-names = "pwr", "core";
|
||||
max-link-speed = <4>;
|
||||
msi-parent = <&its 0>;
|
||||
msi-map = <0x0 &its 0x0 0x10000>;
|
||||
|
|
@ -903,8 +903,8 @@ pciec0_ep: pcie-ep@e65d0000 {
|
|||
clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
|
||||
clock-names = "core", "ref";
|
||||
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 624>;
|
||||
reset-names = "pwr";
|
||||
resets = <&cpg 624>, <&cpg 1121>;
|
||||
reset-names = "pwr", "core";
|
||||
max-link-speed = <4>;
|
||||
num-lanes = <2>;
|
||||
max-functions = /bits/ 8 <2>;
|
||||
|
|
@ -926,8 +926,8 @@ pciec1_ep: pcie-ep@e65d8000 {
|
|||
clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>;
|
||||
clock-names = "core", "ref";
|
||||
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 625>;
|
||||
reset-names = "pwr";
|
||||
resets = <&cpg 625>, <&cpg 1122>;
|
||||
reset-names = "pwr", "core";
|
||||
max-link-speed = <4>;
|
||||
num-lanes = <2>;
|
||||
max-functions = /bits/ 8 <2>;
|
||||
|
|
|
|||
|
|
@ -688,8 +688,8 @@ pciec0: pcie@e65d0000 {
|
|||
clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
|
||||
clock-names = "core", "ref";
|
||||
power-domains = <&sysc R8A779H0_PD_A2PCIPHY>;
|
||||
resets = <&cpg 624>;
|
||||
reset-names = "pwr";
|
||||
resets = <&cpg 624>, <&cpg 1121>;
|
||||
reset-names = "pwr", "core";
|
||||
max-link-speed = <4>;
|
||||
msi-parent = <&its 0>;
|
||||
msi-map = <0x0 &its 0x0 0x10000>;
|
||||
|
|
@ -726,8 +726,8 @@ pciec0_ep: pcie-ep@e65d0000 {
|
|||
clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
|
||||
clock-names = "core", "ref";
|
||||
power-domains = <&sysc R8A779H0_PD_A2PCIPHY>;
|
||||
resets = <&cpg 624>;
|
||||
reset-names = "pwr";
|
||||
resets = <&cpg 624>, <&cpg 1121>;
|
||||
reset-names = "pwr", "core";
|
||||
max-link-speed = <4>;
|
||||
num-lanes = <2>;
|
||||
max-functions = /bits/ 8 <2>;
|
||||
|
|
|
|||
|
|
@ -134,18 +134,18 @@ ecc@18cccc0000 {
|
|||
no-map;
|
||||
};
|
||||
|
||||
ecc@1a66660000 {
|
||||
reg = <0x1a 0x66660000 0x0 0x999a0000>;
|
||||
ecc@1acccc0000 {
|
||||
reg = <0x1a 0xcccc0000 0x0 0x33340000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
ecc@1c66660000 {
|
||||
reg = <0x1c 0x66660000 0x0 0x999a0000>;
|
||||
ecc@1ccccc0000 {
|
||||
reg = <0x1c 0xcccc0000 0x0 0x33340000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
ecc@1e66660000 {
|
||||
reg = <0x1e 0x66660000 0x0 0x999a0000>;
|
||||
ecc@1ecccc0000 {
|
||||
reg = <0x1e 0xcccc0000 0x0 0x33340000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -862,6 +862,118 @@ gic: interrupt-controller@39000000 {
|
|||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2c1: i2c@c06c0000 {
|
||||
compatible = "renesas,i2c-r8a78000",
|
||||
"renesas,rcar-gen5-i2c";
|
||||
reg = <0 0xc06c0000 0 0x40>;
|
||||
interrupts = <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
clocks = <&cpg R8A78000_CPG_SGASYNCD8_PERW_BUS>;
|
||||
power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x44>;
|
||||
resets = <&mdlc_perw 0x44>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@c06c8000 {
|
||||
compatible = "renesas,i2c-r8a78000",
|
||||
"renesas,rcar-gen5-i2c";
|
||||
reg = <0 0xc06c8000 0 0x40>;
|
||||
interrupts = <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
clocks = <&cpg R8A78000_CPG_SGASYNCD8_PERW_BUS>;
|
||||
power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x45>;
|
||||
resets = <&mdlc_perw 0x45>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@c06d0000 {
|
||||
compatible = "renesas,i2c-r8a78000",
|
||||
"renesas,rcar-gen5-i2c";
|
||||
reg = <0 0xc06d0000 0 0x40>;
|
||||
interrupts = <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
clocks = <&cpg R8A78000_CPG_SGASYNCD8_PERW_BUS>;
|
||||
power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x46>;
|
||||
resets = <&mdlc_perw 0x46>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@c06d8000 {
|
||||
compatible = "renesas,i2c-r8a78000",
|
||||
"renesas,rcar-gen5-i2c";
|
||||
reg = <0 0xc06d8000 0 0x40>;
|
||||
interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
clocks = <&cpg R8A78000_CPG_SGASYNCD8_PERW_BUS>;
|
||||
power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x47>;
|
||||
resets = <&mdlc_perw 0x47>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c5: i2c@c06e0000 {
|
||||
compatible = "renesas,i2c-r8a78000",
|
||||
"renesas,rcar-gen5-i2c";
|
||||
reg = <0 0xc06e0000 0 0x40>;
|
||||
interrupts = <GIC_ESPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
clocks = <&cpg R8A78000_CPG_SGASYNCD8_PERW_BUS>;
|
||||
power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x48>;
|
||||
resets = <&mdlc_perw 0x48>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c6: i2c@c06e8000 {
|
||||
compatible = "renesas,i2c-r8a78000",
|
||||
"renesas,rcar-gen5-i2c";
|
||||
reg = <0 0xc06e8000 0 0x40>;
|
||||
interrupts = <GIC_ESPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
clocks = <&cpg R8A78000_CPG_SGASYNCD8_PERW_BUS>;
|
||||
power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x49>;
|
||||
resets = <&mdlc_perw 0x49>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c7: i2c@c06f0000 {
|
||||
compatible = "renesas,i2c-r8a78000",
|
||||
"renesas,rcar-gen5-i2c";
|
||||
reg = <0 0xc06f0000 0 0x40>;
|
||||
interrupts = <GIC_ESPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
clocks = <&cpg R8A78000_CPG_SGASYNCD8_PERW_BUS>;
|
||||
power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x4a>;
|
||||
resets = <&mdlc_perw 0x4a>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c8: i2c@c06f8000 {
|
||||
compatible = "renesas,i2c-r8a78000",
|
||||
"renesas,rcar-gen5-i2c";
|
||||
reg = <0 0xc06f8000 0 0x40>;
|
||||
interrupts = <GIC_ESPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
clocks = <&cpg R8A78000_CPG_SGASYNCD8_PERW_BUS>;
|
||||
power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x4b>;
|
||||
resets = <&mdlc_perw 0x4b>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif0: serial@c0700000 {
|
||||
compatible = "renesas,scif-r8a78000",
|
||||
"renesas,rcar-gen5-scif", "renesas,scif";
|
||||
|
|
@ -1215,6 +1327,110 @@ mdlc_vips: system-controller@c3460000 {
|
|||
#reset-cells = <1>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
msiof0: spi@c1700000 {
|
||||
compatible = "renesas,msiof-r8a78000",
|
||||
"renesas,rcar-gen5-msiof";
|
||||
reg = <0 0xc1700000 0 0x100>;
|
||||
interrupts = <GIC_ESPI 744 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg R8A78000_CPG_MSO_SCP_MAIN>;
|
||||
power-domains = <&mdlc_scp R8A78000_MDLC_PD_SCP 0x50>;
|
||||
resets = <&mdlc_scp 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
msiof1: spi@c1710000 {
|
||||
compatible = "renesas,msiof-r8a78000",
|
||||
"renesas,rcar-gen5-msiof";
|
||||
reg = <0 0xc1710000 0 0x100>;
|
||||
interrupts = <GIC_ESPI 745 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg R8A78000_CPG_MSO_SCP_MAIN>;
|
||||
power-domains = <&mdlc_scp R8A78000_MDLC_PD_SCP 0x51>;
|
||||
resets = <&mdlc_scp 0x51>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
msiof2: spi@c1720000 {
|
||||
compatible = "renesas,msiof-r8a78000",
|
||||
"renesas,rcar-gen5-msiof";
|
||||
reg = <0 0xc1720000 0 0x100>;
|
||||
interrupts = <GIC_ESPI 746 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg R8A78000_CPG_MSO_SCP_MAIN>;
|
||||
power-domains = <&mdlc_scp R8A78000_MDLC_PD_SCP 0x52>;
|
||||
resets = <&mdlc_scp 0x52>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
msiof3: spi@c1730000 {
|
||||
compatible = "renesas,msiof-r8a78000",
|
||||
"renesas,rcar-gen5-msiof";
|
||||
reg = <0 0xc1730000 0 0x100>;
|
||||
interrupts = <GIC_ESPI 747 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg R8A78000_CPG_MSO_SCP_MAIN>;
|
||||
power-domains = <&mdlc_scp R8A78000_MDLC_PD_SCP 0x53>;
|
||||
resets = <&mdlc_scp 0x53>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
msiof4: spi@c0600000 {
|
||||
compatible = "renesas,msiof-r8a78000",
|
||||
"renesas,rcar-gen5-msiof";
|
||||
reg = <0 0xc0600000 0 0x100>;
|
||||
interrupts = <GIC_ESPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg R8A78000_CPG_MSOCK_PERW_BUS>;
|
||||
power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x4f>;
|
||||
resets = <&mdlc_perw 0x4f>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
msiof5: spi@c0608000 {
|
||||
compatible = "renesas,msiof-r8a78000",
|
||||
"renesas,rcar-gen5-msiof";
|
||||
reg = <0 0xc0608000 0 0x100>;
|
||||
interrupts = <GIC_ESPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg R8A78000_CPG_MSOCK_PERW_BUS>;
|
||||
power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x50>;
|
||||
resets = <&mdlc_perw 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
msiof6: spi@c0610000 {
|
||||
compatible = "renesas,msiof-r8a78000",
|
||||
"renesas,rcar-gen5-msiof";
|
||||
reg = <0 0xc0610000 0 0x100>;
|
||||
interrupts = <GIC_ESPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg R8A78000_CPG_MSOCK_PERW_BUS>;
|
||||
power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x51>;
|
||||
resets = <&mdlc_perw 0x51>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
msiof7: spi@c0618000 {
|
||||
compatible = "renesas,msiof-r8a78000",
|
||||
"renesas,rcar-gen5-msiof";
|
||||
reg = <0 0xc0618000 0 0x100>;
|
||||
interrupts = <GIC_ESPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg R8A78000_CPG_MSOCK_PERW_BUS>;
|
||||
power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x52>;
|
||||
resets = <&mdlc_perw 0x52>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,89 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Description for SolidRun RZ/G2UL Type-2 HummingBoard Ripple.
|
||||
*
|
||||
* Copyright 2025 Josua Mayer <josua@solid-run.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "r9a07g043u.dtsi"
|
||||
#include "rzg2ul-sr-som.dtsi"
|
||||
#include "rzg2l-hummingboard-pulse-common.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "solidrun,rzg2ul-hummingboard-ripple", "solidrun,rzg2ul-sr-som",
|
||||
"renesas,r9a07g043u12", "renesas,r9a07g043";
|
||||
model = "SolidRun RZ/G2UL HummingBoard Ripple";
|
||||
|
||||
leds: leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led-0 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
default-state = "on";
|
||||
gpios = <&pinctrl RZG2L_GPIO(12, 1) GPIO_ACTIVE_LOW>;
|
||||
label = "D30";
|
||||
};
|
||||
};
|
||||
|
||||
vbus1: regulator-vbus-1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vbus1";
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
gpios = <&pinctrl RZG2L_GPIO(5, 2) GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
&hub_2_0 {
|
||||
reset-gpios = <&pinctrl RZG2L_GPIO(13, 3) GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
hdmi_pd_hog: hdmi-pd-hog {
|
||||
/*
|
||||
* RZ/G2UL does not have DSI output to feed DSI-to-HDMI
|
||||
* bridge. Keep its shutdown signal asserted.
|
||||
*/
|
||||
gpio-hog;
|
||||
gpios = <RZG2L_GPIO(14, 2) GPIO_ACTIVE_LOW>;
|
||||
line-name = "hdmi-pd";
|
||||
output-high;
|
||||
};
|
||||
|
||||
mpcie_rst_hog: mpcie-reset-hog {
|
||||
gpio-hog;
|
||||
gpios = <RZG2L_GPIO(0, 3) GPIO_ACTIVE_LOW>;
|
||||
line-name = "mpcie-reset";
|
||||
output-low;
|
||||
};
|
||||
|
||||
mikro_uart_pins: pinctrl-mikro-uart-grp {
|
||||
pinmux = <RZG2L_PORT_PINMUX(14, 1, 1)>, /* SCIF1_RXD */
|
||||
<RZG2L_PORT_PINMUX(14, 0, 1)>; /* SCIF1_TXD */
|
||||
};
|
||||
|
||||
usb0_vbus_pins: usb0-vbus {
|
||||
pinmux = <RZG2L_PORT_PINMUX(5, 0, 1)>; /* USB0_VBUSEN */
|
||||
};
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
vbus-supply = <&vbus1>;
|
||||
};
|
||||
|
||||
&vmmc {
|
||||
gpios = <&pinctrl RZG2L_GPIO(0, 1) GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&vmpcie {
|
||||
/*
|
||||
* G2UL SoM v1.2 moved this IO from J7-28 (CON4-12)
|
||||
* to J7-18 (this regulator).
|
||||
* There are no known users of CON4-12 and thus no need
|
||||
* to differentiate here between SoM v1.1 and v1.2.
|
||||
*/
|
||||
gpios = <&pinctrl RZG2L_GPIO(13, 4) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Copyright 2025 Josua Mayer <josua@solid-run.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "r9a07g044c2.dtsi"
|
||||
#include "rzg2lc-sr-som.dtsi"
|
||||
#include "rzg2l-hummingboard-iiot-common.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "solidrun,rzg2lc-hummingboard-iiot", "solidrun,rzg2lc-sr-som",
|
||||
"renesas,r9a07g044c2", "renesas,r9a07g044";
|
||||
model = "SolidRun RZ/G2LC HummingBoard IIoT";
|
||||
};
|
||||
|
||||
&vmmc {
|
||||
gpios = <&pinctrl RZG2L_GPIO(18, 1) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
|
@ -0,0 +1,93 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Copyright 2025 Josua Mayer <josua@solid-run.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "r9a07g044c2.dtsi"
|
||||
#include "rzg2lc-sr-som.dtsi"
|
||||
#include "rzg2l-hummingboard-pulse-common.dtsi"
|
||||
#include "rzg2l-hummingboard-pulse-micro-hdmi.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "solidrun,rzg2lc-hummingboard-ripple", "solidrun,rzg2lc-sr-som",
|
||||
"renesas,r9a07g044c2", "renesas,r9a07g044";
|
||||
model = "SolidRun RZ/G2LC HummingBoard Ripple";
|
||||
|
||||
leds: leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led-0 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
default-state = "on";
|
||||
gpios = <&pinctrl RZG2L_GPIO(0, 1) GPIO_ACTIVE_LOW>;
|
||||
label = "D30";
|
||||
};
|
||||
};
|
||||
|
||||
vbus1: regulator-vbus-1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vbus1";
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
gpios = <&pinctrl RZG2L_GPIO(5, 0) GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
&gpt {
|
||||
/* mikrobus header pwm pin is pwm channel 6 */
|
||||
pinctrl-0 = <&mikro_pwm_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
interrupts-extended = <&pinctrl RZG2L_GPIO(42, 2) IRQ_TYPE_EDGE_FALLING>;
|
||||
pd-gpios = <&pinctrl RZG2L_GPIO(40, 2) GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&hub_2_0 {
|
||||
reset-gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
mpcie_rst_hog: mpcie-reset-hog {
|
||||
gpios = <RZG2L_GPIO(19, 1) GPIO_ACTIVE_LOW>;
|
||||
gpio-hog;
|
||||
line-name = "mpcie-reset";
|
||||
output-low;
|
||||
};
|
||||
|
||||
mikro_pwm_pins: pinctrl-mikro-pwm-grp {
|
||||
pinmux = <RZG2L_PORT_PINMUX(41, 0, 4)>; /* GTIOC3A */
|
||||
};
|
||||
|
||||
mikro_uart_pins: pinctrl-mikro-uart-grp {
|
||||
pinmux = <RZG2L_PORT_PINMUX(40, 1, 1)>, /* SCIF1_RXD */
|
||||
<RZG2L_PORT_PINMUX(40, 0, 1)>; /* SCIF1_TXD */
|
||||
};
|
||||
|
||||
usb0_vbus_pins: usb0-vbus {
|
||||
pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>; /* USB0_VBUSEN */
|
||||
};
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
vbus-supply = <&vbus1>;
|
||||
};
|
||||
|
||||
&vmmc {
|
||||
gpios = <&pinctrl RZG2L_GPIO(18, 1) GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&vmpcie {
|
||||
/*
|
||||
* G2LC SoM v1.2 moved this IO from J7-28 (CON4-12)
|
||||
* to J7-18 (this regulator).
|
||||
* There are no known users of CON4-12 and thus no need
|
||||
* to differentiate here between SoM v1.1 and v1.2.
|
||||
*/
|
||||
gpios = <&pinctrl RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Copyright 2025 Josua Mayer <josua@solid-run.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "r9a07g044l2.dtsi"
|
||||
#include "rzg2l-sr-som.dtsi"
|
||||
#include "rzg2l-hummingboard-iiot.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "solidrun,rzg2l-hummingboard-iiot", "solidrun,rzg2l-sr-som",
|
||||
"renesas,r9a07g044l2", "renesas,r9a07g044";
|
||||
model = "SolidRun RZ/G2L HummingBoard IIoT";
|
||||
};
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Copyright 2025 Josua Mayer <josua@solid-run.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "r9a07g044l2.dtsi"
|
||||
#include "rzg2l-sr-som.dtsi"
|
||||
#include "rzg2l-hummingboard-pulse-common.dtsi"
|
||||
#include "rzg2l-hummingboard-pulse-micro-hdmi.dtsi"
|
||||
#include "rzg2l-hummingboard-ripple.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "solidrun,rzg2l-hummingboard-ripple", "solidrun,rzg2l-sr-som",
|
||||
"renesas,r9a07g044l2", "renesas,r9a07g044";
|
||||
model = "SolidRun RZ/G2L HummingBoard Ripple";
|
||||
};
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Copyright 2025 Josua Mayer <josua@solid-run.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "r9a07g054l2.dtsi"
|
||||
#include "rzg2l-sr-som.dtsi"
|
||||
#include "rzg2l-hummingboard-iiot.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "solidrun,rzv2l-hummingboard-iiot", "solidrun,rzv2l-sr-som",
|
||||
"renesas,r9a07g054l2", "renesas,r9a07g054";
|
||||
model = "SolidRun RZ/V2L HummingBoard IIoT";
|
||||
};
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Copyright 2025 Josua Mayer <josua@solid-run.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "r9a07g054l2.dtsi"
|
||||
#include "rzg2l-sr-som.dtsi"
|
||||
#include "rzg2l-hummingboard-pulse-common.dtsi"
|
||||
#include "rzg2l-hummingboard-pulse-micro-hdmi.dtsi"
|
||||
#include "rzg2l-hummingboard-ripple.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "solidrun,rzv2l-hummingboard-ripple", "solidrun,rzv2l-sr-som",
|
||||
"renesas,r9a07g054l2", "renesas,r9a07g054";
|
||||
model = "SolidRun RZ/V2L HummingBoard Ripple";
|
||||
};
|
||||
|
|
@ -1266,21 +1266,87 @@ queue3 {
|
|||
};
|
||||
};
|
||||
|
||||
ohci0: usb@11e10000 {
|
||||
reg = <0 0x11e10000 0 0x100>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
ohci1: usb@11e90000 {
|
||||
reg = <0 0x11e90000 0 0x100>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
ehci0: usb@11e10100 {
|
||||
reg = <0 0x11e10100 0 0x100>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
ehci1: usb@11e90100 {
|
||||
reg = <0 0x11e90100 0 0x100>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
hsusb0: usb@11e30000 {
|
||||
reg = <0 0x11e30000 0 0x10000>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
pcie: pcie@11e40000 {
|
||||
compatible = "renesas,r9a08g046-pcie";
|
||||
reg = <0 0x11e40000 0 0x10000>;
|
||||
ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>;
|
||||
/* Map all possible DRAM ranges (4 GB). */
|
||||
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 1 0x00000000>;
|
||||
bus-range = <0x0 0xff>;
|
||||
interrupts = <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 484 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "serr", "serr_cor", "serr_nonfatal",
|
||||
"serr_fatal", "axi_err", "inta",
|
||||
"intb", "intc", "intd", "msi",
|
||||
"link_bandwidth", "pm_pme", "dma",
|
||||
"pcie_evt", "msg", "all";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie 0 0 0 0>, /* INTA */
|
||||
<0 0 0 2 &pcie 0 0 0 1>, /* INTB */
|
||||
<0 0 0 3 &pcie 0 0 0 2>, /* INTC */
|
||||
<0 0 0 4 &pcie 0 0 0 3>; /* INTD */
|
||||
clocks = <&cpg CPG_MOD R9A08G046_PCI_ACLK>,
|
||||
<&cpg CPG_MOD R9A08G046_PCI_CLKL1PM>,
|
||||
<&cpg CPG_MOD R9A08G046_PCI_CLK_PMU>;
|
||||
clock-names = "aclk", "pm", "pmu";
|
||||
resets = <&cpg R9A08G046_PCI_ARESETN>;
|
||||
reset-names = "aresetn";
|
||||
power-domains = <&cpg>;
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
/* placeholder */
|
||||
renesas,sysc = <&sysc>;
|
||||
status = "disabled";
|
||||
|
||||
pcie_port0: pcie@0,0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
ranges;
|
||||
device_type = "pci";
|
||||
vendor-id = <0x1912>;
|
||||
device-id = <0x0033>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
/* placeholder */
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -71,6 +71,18 @@ codec_dai: codec {
|
|||
#endif
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&ehci1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&hsusb0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -122,6 +134,19 @@ &keys {
|
|||
#endif
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&ohci1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie {
|
||||
pinctrl-0 = <&pcie_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
audio_clk_pins: audio-clock {
|
||||
pinmux = <RZG3L_PORT_PINMUX(H, 4, 6)>, /* AUDIO_CLK_B */
|
||||
|
|
@ -138,6 +163,17 @@ i2c3_pins: i2c3 {
|
|||
<RZG3L_PORT_PINMUX(2, 1, 4)>; /* RIIC3_SDA */
|
||||
};
|
||||
|
||||
pcie-clkreq-n-hog {
|
||||
gpio-hog;
|
||||
gpios = <RZG3L_GPIO(G, 6) GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "PCIE_A_CKREQ";
|
||||
};
|
||||
|
||||
pcie_pins: pcie {
|
||||
pinmux = <RZG3L_PORT_PINMUX(G, 7, 1)>; /* PCIE_RST_OUT# */
|
||||
};
|
||||
|
||||
rsci1_pins: rsci1 {
|
||||
pinmux = <RZG3L_PORT_PINMUX(D, 4, 5)>, /* RSCI1_RXD_MISO_SCL */
|
||||
<RZG3L_PORT_PINMUX(D, 5, 5)>, /* RSCI1_TXD_MOSI_SDA */
|
||||
|
|
|
|||
|
|
@ -1743,6 +1743,130 @@ gic: interrupt-controller@14900000 {
|
|||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
ohci0: usb@15800000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0 0x15800000 0 0x100>;
|
||||
interrupts = <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>;
|
||||
resets = <&usb20phyrst>, <&cpg 0xac>;
|
||||
phys = <&usb2_phy0 1>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci1: usb@15810000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0 0x15810000 0 0x100>;
|
||||
interrupts = <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>;
|
||||
resets = <&usb21phyrst>, <&cpg 0xad>;
|
||||
phys = <&usb2_phy1 1>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci0: usb@15800100 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0 0x15800100 0 0x100>;
|
||||
interrupts = <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>;
|
||||
resets = <&usb20phyrst>, <&cpg 0xac>;
|
||||
phys = <&usb2_phy0 2>;
|
||||
phy-names = "usb";
|
||||
companion = <&ohci0>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci1: usb@15810100 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0 0x15810100 0 0x100>;
|
||||
interrupts = <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>;
|
||||
resets = <&usb21phyrst>, <&cpg 0xad>;
|
||||
phys = <&usb2_phy1 2>;
|
||||
phy-names = "usb";
|
||||
companion = <&ohci1>;
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2_phy0: usb-phy@15800200 {
|
||||
compatible = "renesas,usb2-phy-r9a09g047",
|
||||
"renesas,usb2-phy-r9a09g057";
|
||||
reg = <0 0x15800200 0 0x700>;
|
||||
interrupts = <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 0xb3>,
|
||||
<&cpg CPG_CORE R9A09G047_USB2_0_CLK_CORE0>;
|
||||
clock-names = "fck", "usb_x1";
|
||||
resets = <&usb20phyrst>, <&cpg 0xac>;
|
||||
#phy-cells = <1>;
|
||||
power-domains = <&cpg>;
|
||||
mux-states = <&usb20phyrst 1>;
|
||||
status = "disabled";
|
||||
|
||||
usb2_phy0_vbus_otg: vbus-regulator {
|
||||
regulator-name = "USB2PHY0-VBUS-OTG";
|
||||
};
|
||||
};
|
||||
|
||||
usb2_phy1: usb-phy@15810200 {
|
||||
compatible = "renesas,usb2-phy-r9a09g047",
|
||||
"renesas,usb2-phy-r9a09g057";
|
||||
reg = <0 0x15810200 0 0x700>;
|
||||
interrupts = <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 0xb4>,
|
||||
<&cpg CPG_CORE R9A09G047_USB2_0_CLK_CORE1>;
|
||||
clock-names = "fck", "usb_x1";
|
||||
resets = <&usb21phyrst>, <&cpg 0xad>;
|
||||
#phy-cells = <1>;
|
||||
power-domains = <&cpg>;
|
||||
mux-states = <&usb21phyrst 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsusb0: usb@15820000 {
|
||||
compatible = "renesas,usbhs-r9a09g047",
|
||||
"renesas,rzg2l-usbhs";
|
||||
reg = <0 0x15820000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 751 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb5>;
|
||||
resets = <&usb20phyrst>, <&cpg 0xae>;
|
||||
phys = <&usb2_phy0 3>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&cpg>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb20phyrst: reset-controller@15830000 {
|
||||
compatible = "renesas,r9a09g047-usb2phy-reset",
|
||||
"renesas,r9a09g057-usb2phy-reset";
|
||||
reg = <0 0x15830000 0 0x10000>;
|
||||
clocks = <&cpg CPG_MOD 0xb6>;
|
||||
resets = <&cpg 0xaf>;
|
||||
power-domains = <&cpg>;
|
||||
#reset-cells = <0>;
|
||||
#mux-state-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb21phyrst: reset-controller@15840000 {
|
||||
compatible = "renesas,r9a09g047-usb2phy-reset",
|
||||
"renesas,r9a09g057-usb2phy-reset";
|
||||
reg = <0 0x15840000 0 0x10000>;
|
||||
clocks = <&cpg CPG_MOD 0xb7>;
|
||||
resets = <&cpg 0xaf>;
|
||||
power-domains = <&cpg>;
|
||||
#reset-cells = <0>;
|
||||
#mux-state-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
xhci: usb@15850000 {
|
||||
compatible = "renesas,r9a09g047-xhci";
|
||||
reg = <0 0x15850000 0 0x10000>;
|
||||
|
|
|
|||
|
|
@ -301,6 +301,17 @@ sd1-data {
|
|||
};
|
||||
};
|
||||
|
||||
usb20_pins: usb20 {
|
||||
ovc {
|
||||
pinmux = <RZG3E_PORT_PINMUX(0, 0, 12)>; /* USB20_OVRCURN */
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
vbus {
|
||||
pinmux = <RZG3E_PORT_PINMUX(0, 1, 12)>; /* USB20_VBUSEN */
|
||||
};
|
||||
};
|
||||
|
||||
usb3_pins: usb3 {
|
||||
pinmux = <RZG3E_PORT_PINMUX(4, 1, 12)>, /* USB30_VBUSEN */
|
||||
<RZG3E_PORT_PINMUX(4, 0, 12)>; /* USB30_OVRCURN */
|
||||
|
|
@ -397,6 +408,26 @@ &ssi4 {
|
|||
shared-pin;
|
||||
};
|
||||
|
||||
&usb20phyrst {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb21phyrst {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy0 {
|
||||
pinctrl-0 = <&usb20_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vbus-supply = <&usb2_phy0_vbus_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1271,14 +1271,14 @@ adc0: adc@90014000 {
|
|||
<GIC_SPI 699 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 700 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 701 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 851 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 852 IRQ_TYPE_EDGE_RISING>;
|
||||
<GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "adi", "gbadi", "gcadi",
|
||||
"cmpai", "cmpbi", "wcmpm", "wcmpum";
|
||||
"cmpai", "cmpbi";
|
||||
clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>,
|
||||
<&cpg CPG_MOD 206>;
|
||||
clock-names = "adclk", "pclk";
|
||||
dmas = <&dmac0 0x26ba>, <&dmac1 0x26ba>, <&dmac2 0x26ba>;
|
||||
dma-names = "rx", "rx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -1293,14 +1293,14 @@ adc1: adc@90014400 {
|
|||
<GIC_SPI 704 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 705 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 853 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 854 IRQ_TYPE_EDGE_RISING>;
|
||||
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "adi", "gbadi", "gcadi",
|
||||
"cmpai", "cmpbi", "wcmpm", "wcmpum";
|
||||
"cmpai", "cmpbi";
|
||||
clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>,
|
||||
<&cpg CPG_MOD 207>;
|
||||
clock-names = "adclk", "pclk";
|
||||
dmas = <&dmac0 0x26bf>, <&dmac1 0x26bf>, <&dmac2 0x26bf>;
|
||||
dma-names = "rx", "rx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -1315,14 +1315,14 @@ adc2: adc@80008000 {
|
|||
<GIC_SPI 709 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 710 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 855 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 856 IRQ_TYPE_EDGE_RISING>;
|
||||
<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "adi", "gbadi", "gcadi",
|
||||
"cmpai", "cmpbi", "wcmpm", "wcmpum";
|
||||
"cmpai", "cmpbi";
|
||||
clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>,
|
||||
<&cpg CPG_MOD 225>;
|
||||
clock-names = "adclk", "pclk";
|
||||
dmas = <&dmac0 0x26c4>, <&dmac1 0x26c4>, <&dmac2 0x26c4>;
|
||||
dma-names = "rx", "rx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -1274,14 +1274,14 @@ adc0: adc@90014000 {
|
|||
<GIC_SPI 699 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 700 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 701 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 851 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 852 IRQ_TYPE_EDGE_RISING>;
|
||||
<GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "adi", "gbadi", "gcadi",
|
||||
"cmpai", "cmpbi", "wcmpm", "wcmpum";
|
||||
"cmpai", "cmpbi";
|
||||
clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>,
|
||||
<&cpg CPG_MOD 206>;
|
||||
clock-names = "adclk", "pclk";
|
||||
dmas = <&dmac0 0x26ba>, <&dmac1 0x26ba>, <&dmac2 0x26ba>;
|
||||
dma-names = "rx", "rx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -1296,14 +1296,14 @@ adc1: adc@90014400 {
|
|||
<GIC_SPI 704 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 705 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 853 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 854 IRQ_TYPE_EDGE_RISING>;
|
||||
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "adi", "gbadi", "gcadi",
|
||||
"cmpai", "cmpbi", "wcmpm", "wcmpum";
|
||||
"cmpai", "cmpbi";
|
||||
clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>,
|
||||
<&cpg CPG_MOD 207>;
|
||||
clock-names = "adclk", "pclk";
|
||||
dmas = <&dmac0 0x26bf>, <&dmac1 0x26bf>, <&dmac2 0x26bf>;
|
||||
dma-names = "rx", "rx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -1318,14 +1318,14 @@ adc2: adc@80008000 {
|
|||
<GIC_SPI 709 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 710 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 855 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 856 IRQ_TYPE_EDGE_RISING>;
|
||||
<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "adi", "gbadi", "gcadi",
|
||||
"cmpai", "cmpbi", "wcmpm", "wcmpum";
|
||||
"cmpai", "cmpbi";
|
||||
clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>,
|
||||
<&cpg CPG_MOD 225>;
|
||||
clock-names = "adclk", "pclk";
|
||||
dmas = <&dmac0 0x26c4>, <&dmac1 0x26c4>, <&dmac2 0x26c4>;
|
||||
dma-names = "rx", "rx", "rx";
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -84,11 +84,36 @@ &canfd {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci1 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hsusb0 {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci1 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
560
arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-common.dtsi
Normal file
560
arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot-common.dtsi
Normal file
|
|
@ -0,0 +1,560 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Copyright 2025 Josua Mayer <josua@solid-run.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
/ {
|
||||
/* power for M.2 B-Key connector (J6) */
|
||||
regulator-m2-b {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "m2-b";
|
||||
gpios = <&tca6416_u20 5 GPIO_ACTIVE_HIGH>;
|
||||
regulator-always-on;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
/* power for M.2 M-Key connector (J4) */
|
||||
regulator-m2-m {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "m2-m";
|
||||
gpios = <&tca6416_u20 6 GPIO_ACTIVE_HIGH>;
|
||||
regulator-always-on;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
/* power for USB-A J27 behind USB Hub Port 3 */
|
||||
regulator-vbus-2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vbus2";
|
||||
regulator-always-on;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
gpios = <&tca6416_u20 12 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
/* power for USB-A J27 behind USB Hub Port 4 */
|
||||
regulator-vbus-3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vbus3";
|
||||
regulator-always-on;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
gpios = <&tca6416_u20 13 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
aliases {
|
||||
i2c3 = &i2c_exp;
|
||||
i2c4 = &i2c_csi;
|
||||
i2c5 = &i2c_dsi;
|
||||
i2c6 = &i2c_lvds;
|
||||
rtc0 = &carrier_rtc;
|
||||
rtc1 = &pmic;
|
||||
serial3 = &scif3;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
wakeup-event {
|
||||
interrupts-extended = <&tca6416_u21 11 IRQ_TYPE_EDGE_FALLING>;
|
||||
label = "m2-m-wakeup";
|
||||
wakeup-source;
|
||||
linux,code = <KEY_WAKEUP>;
|
||||
};
|
||||
};
|
||||
|
||||
can_mux: mux-controller-1 {
|
||||
compatible = "gpio-mux";
|
||||
/* default J9-55/57/59/61 to on-board transceivers */
|
||||
idle-state = <0>;
|
||||
#mux-control-cells = <0>;
|
||||
/*
|
||||
* Mux routes CAN bus signals between SoM connector pins,
|
||||
* expansion connector (J22) and on-board transceivers using
|
||||
* two GPIO:
|
||||
* - IO3: 0 = on-board transceivers, 1 = expansion connector
|
||||
* - IO4: 0 = J9-55/57/59/61, 1 = J7-12/16 & J9-54/56
|
||||
*/
|
||||
mux-gpios = <&tca6416_u20 3 GPIO_ACTIVE_HIGH>,
|
||||
<&tca6416_u20 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
spi_mux: mux-controller-2 {
|
||||
compatible = "gpio-mux";
|
||||
/* default on-board */
|
||||
idle-state = <0>;
|
||||
/*
|
||||
* Mux switches spi bus between on-board tpm
|
||||
* and expansion connector (J22).
|
||||
*/
|
||||
mux-gpios = <&tca6416_u21 0 GPIO_ACTIVE_HIGH>;
|
||||
#mux-control-cells = <0>;
|
||||
};
|
||||
|
||||
scif1_scif3_b2b_mux: mux-controller-3 {
|
||||
compatible = "gpio-mux";
|
||||
/* default on-board */
|
||||
idle-state = <0>;
|
||||
#mux-control-cells = <0>;
|
||||
/*
|
||||
* Mux switches both scif1 and scif3 tx/rx between expansion
|
||||
* connector (J22) and on-board rs232/rs485 transceivers
|
||||
* using one GPIO: 0 = on-board, 1 = connector.
|
||||
*/
|
||||
mux-gpios = <&tca6416_u20 0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
scif1_rs_232_485_mux: mux-controller-4 {
|
||||
compatible = "gpio-mux";
|
||||
/* default rs232 */
|
||||
idle-state = <0>;
|
||||
#mux-control-cells = <0>;
|
||||
/*
|
||||
* Mux switches scif1 tx/rx between rs232 and rs485
|
||||
* transceivers. using one GPIO: 0 = rs232, 1 = rs485.
|
||||
*/
|
||||
mux-gpios = <&tca6416_u20 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
scif3_rs_232_485_mux: mux-controller-5 {
|
||||
compatible = "gpio-mux";
|
||||
/* default rs232 */
|
||||
idle-state = <0>;
|
||||
#mux-control-cells = <0>;
|
||||
/*
|
||||
* Mux switches scif3 tx/rx between rs232 and rs485
|
||||
* transceivers. using one GPIO: 0 = rs232, 1 = rs485.
|
||||
*/
|
||||
mux-gpios = <&tca6416_u20 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
v_1_2: regulator-1v2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "1v2";
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-min-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
v_3_3: regulator-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3v3";
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
reg_dsi_panel: regulator-dsi-panel {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dsi-panel";
|
||||
gpios = <&tca6416_u20 15 GPIO_ACTIVE_HIGH>;
|
||||
regulator-max-microvolt = <11200000>;
|
||||
regulator-min-microvolt = <11200000>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vmmc: regulator-mmc {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmc";
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
startup-delay-us = <250>;
|
||||
vin-supply = <&v_3_3>;
|
||||
gpios = <&pinctrl RZG2L_GPIO(4, 1) GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
/* power for USB-A J5003 */
|
||||
vbus1: regulator-vbus-1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vbus1";
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
gpios = <&tca6416_u20 14 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
rfkill-m2-b-gnss {
|
||||
compatible = "rfkill-gpio";
|
||||
/* rfkill-gpio inverts internally */
|
||||
shutdown-gpios = <&tca6416_u20 10 GPIO_ACTIVE_LOW>;
|
||||
label = "m2-b gnss";
|
||||
radio-type = "gps";
|
||||
};
|
||||
|
||||
rfkill-m2-b-wwan {
|
||||
compatible = "rfkill-gpio";
|
||||
/* rfkill-gpio inverts internally */
|
||||
shutdown-gpios = <&tca6416_u20 9 GPIO_ACTIVE_HIGH>;
|
||||
label = "m2-b radio";
|
||||
radio-type = "wwan";
|
||||
};
|
||||
};
|
||||
|
||||
&ehci1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
hub_2_0: hub@1 {
|
||||
compatible = "usb4b4,6502", "usb4b4,6506";
|
||||
reg = <1>;
|
||||
reset-gpios = <&tca6416_u20 11 GPIO_ACTIVE_LOW>;
|
||||
vdd2-supply = <&v_3_3>;
|
||||
vdd-supply = <&v_1_2>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
/* highest i2c clock supported by all peripherals is 400kHz */
|
||||
|
||||
tca6416_u20: gpio@20 {
|
||||
compatible = "ti,tcal6416";
|
||||
reg = <0x20>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-line-names = "TCA_INT/EXT_UART", "TCA_UARTA_232/485",
|
||||
"TCA_UARTB_232/485", "TCA_INT/EXT_CAN",
|
||||
"TCA_NXP/REN", "TCA_M.2B_3V3_EN",
|
||||
"TCA_M.2M_3V3_EN", "TCA_M.2M_RESET#",
|
||||
"TCA_M.2B_RESET#", "TCA_M.2B_W_DIS#",
|
||||
"TCA_M.2B_GPS_EN#", "TCA_USB-HUB_RST#",
|
||||
"TCA_USB_HUB3_PWR_EN", "TCA_USB_HUB4_PWR_EN",
|
||||
"TCA_USB1_PWR_EN", "TCA_VIDEO_PWR_EN";
|
||||
|
||||
m2-b-reset-hog {
|
||||
gpios = <8 GPIO_ACTIVE_LOW>;
|
||||
gpio-hog;
|
||||
line-name = "m2-b-reset";
|
||||
output-low;
|
||||
};
|
||||
|
||||
m2-m-reset-hog {
|
||||
gpios = <7 GPIO_ACTIVE_LOW>;
|
||||
gpio-hog;
|
||||
line-name = "m2-m-reset";
|
||||
/*
|
||||
* M.2 Key-M connector only supports PCI,
|
||||
* but RZ/G2L(C) has no pci controller.
|
||||
* Keep any card in reset.
|
||||
*/
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
tca6416_u21: gpio@21 {
|
||||
compatible = "ti,tcal6416";
|
||||
reg = <0x21>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-line-names = "TCA_SPI_TPM/EXT", "TCA_TPM_RST#",
|
||||
"TCA_I2C_RST", "TCA_RS232_SHTD#",
|
||||
"TCA_LCD_I2C_RST", "TCA_DIG_OUT1",
|
||||
"TCA_bDIG_IN1", "TCA_SENS_INT",
|
||||
"TCA_ALERT#", "TCA_TPM_PIRQ#",
|
||||
"TCA_RTC_INT", "TCA_M.2M_WAKW_ON_LAN",
|
||||
"TCA_M.2M_CLKREQ#", "TCA_LVDS_INT#",
|
||||
"", "TCA_POE_AT";
|
||||
/*
|
||||
* Level interrupts are typical for gpio expander but not supported on rz/g2l
|
||||
* gpios. However since TCAL6416 latches interrupts and clears only on reading
|
||||
* port register, falling edge trigger doesn't lose events.
|
||||
*/
|
||||
interrupts-extended = <&pinctrl RZG2L_GPIO(4, 0) IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
lcd-i2c-reset-hog {
|
||||
gpios = <4 (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>;
|
||||
line-name = "lcd-i2c-reset";
|
||||
output-low;
|
||||
/*
|
||||
* reset shared between U37 and U48, to be
|
||||
* supported once gpio-pca953x switches to
|
||||
* reset framework.
|
||||
*/
|
||||
gpio-hog;
|
||||
};
|
||||
|
||||
lvds-irq-hog {
|
||||
gpios = <13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
|
||||
gpio-hog;
|
||||
input;
|
||||
line-name = "lvds-irq";
|
||||
};
|
||||
|
||||
m2-m-clkreq-hog {
|
||||
gpios = <12 GPIO_ACTIVE_LOW>;
|
||||
gpio-hog;
|
||||
input;
|
||||
line-name = "m2-m-clkreq";
|
||||
};
|
||||
|
||||
rs232_shutdown: rs232-shutdown-hog {
|
||||
gpios = <3 GPIO_ACTIVE_LOW>;
|
||||
gpio-hog;
|
||||
line-name = "rs232-shutdown";
|
||||
output-low;
|
||||
};
|
||||
|
||||
sensor-irq-hog {
|
||||
gpios = <7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
|
||||
gpio-hog;
|
||||
input;
|
||||
line-name = "sensor-irq";
|
||||
};
|
||||
|
||||
tpm-irq-hog {
|
||||
gpios = <9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
|
||||
gpio-hog;
|
||||
input;
|
||||
line-name = "tpm-irq";
|
||||
};
|
||||
};
|
||||
|
||||
led-controller@30 {
|
||||
compatible = "ti,lp5562";
|
||||
reg = <0x30>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
/* use internal clock, could use external generated by rtc */
|
||||
clock-mode = /bits/ 8 <1>;
|
||||
|
||||
multi-led@0 {
|
||||
reg = <0x0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
color = <LED_COLOR_ID_RGB>;
|
||||
label = "D7";
|
||||
|
||||
led@0 {
|
||||
reg = <0x0>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
led-cur = /bits/ 8 <0x32>;
|
||||
max-cur = /bits/ 8 <0x64>;
|
||||
};
|
||||
|
||||
led@1 {
|
||||
reg = <0x1>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
led-cur = /bits/ 8 <0x19>;
|
||||
max-cur = /bits/ 8 <0x32>;
|
||||
};
|
||||
|
||||
led@2 {
|
||||
reg = <0x2>;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
led-cur = /bits/ 8 <0x19>;
|
||||
max-cur = /bits/ 8 <0x32>;
|
||||
};
|
||||
};
|
||||
|
||||
led@3 {
|
||||
reg = <0x3>;
|
||||
chan-name = "D8";
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
label = "D8";
|
||||
led-cur = /bits/ 8 <0x19>;
|
||||
max-cur = /bits/ 8 <0x64>;
|
||||
};
|
||||
};
|
||||
|
||||
light-sensor@44 {
|
||||
compatible = "isil,isl29023";
|
||||
reg = <0x44>;
|
||||
/* IRQ shared between accelerometer, light-sensor and Tamper input (J5007) */
|
||||
interrupts-extended = <&tca6416_u21 7 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
accelerometer@53 {
|
||||
compatible = "adi,adxl345";
|
||||
reg = <0x53>;
|
||||
interrupts-extended = <&tca6416_u21 7 IRQ_TYPE_LEVEL_LOW>;
|
||||
/* IRQ shared between accelerometer, light-sensor and Tamper input (J5007) */
|
||||
interrupt-names = "INT1";
|
||||
};
|
||||
|
||||
carrier_eeprom: eeprom@57 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x57>;
|
||||
pagesize = <8>;
|
||||
};
|
||||
|
||||
carrier_rtc: rtc@69 {
|
||||
compatible = "abracon,ab1805";
|
||||
reg = <0x69>;
|
||||
/*
|
||||
* AM1805 RTC used on this board has only nTIRQ pins wired,
|
||||
* which is for countdown timer irqs only.
|
||||
* Driver does not support this, disable for now.
|
||||
*
|
||||
* interrupts-extended = <&tca6416_u21 10 IRQ_TYPE_LEVEL_LOW>;
|
||||
*/
|
||||
abracon,tc-diode = "schottky";
|
||||
abracon,tc-resistor = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
/* highest i2c clock supported by all peripherals is 400kHz */
|
||||
|
||||
i2c-mux@70 {
|
||||
compatible = "nxp,pca9546";
|
||||
reg = <0x70>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
/*
|
||||
* This reset is open drain with HW 10k pull-up resistor,
|
||||
* but reset core does not support GPIO_OPEN_DRAIN flag.
|
||||
* The pull-up and GPIO voltages match, push-pull is safe.
|
||||
*/
|
||||
reset-gpios = <&tca6416_u21 2 GPIO_ACTIVE_LOW>;
|
||||
|
||||
/* channel 0 routed to expansion connector (J22) */
|
||||
i2c_exp: i2c@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
/* channel 1 routed to mipi-csi connector (J23) */
|
||||
i2c_csi: i2c@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
/* channel 2 routed to mipi-dsi connector (J25) */
|
||||
i2c_dsi: i2c@2 {
|
||||
reg = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tca6408_u48: gpio@21 {
|
||||
compatible = "ti,tca6408";
|
||||
reg = <0x21>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "CAM_RST#", "DSI_RESET",
|
||||
"DSI_STBYB", "DSI_PWM_BL",
|
||||
"DSI_L/R", "DSI_U/D",
|
||||
"DSI_CTP_/RST", "CAM_TRIG";
|
||||
/*
|
||||
* reset shared between U37 and U48, to be
|
||||
* supported once gpio-pca953x switches to
|
||||
* reset framework.
|
||||
*
|
||||
* reset-gpios = <&tca6416_u21 4
|
||||
* (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>;
|
||||
*/
|
||||
gpio-controller;
|
||||
};
|
||||
};
|
||||
|
||||
/* channel 3 routed to lvds connector (J24) */
|
||||
i2c_lvds: i2c@3 {
|
||||
reg = <3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tca6408_u37: gpio@20 {
|
||||
compatible = "ti,tca6408";
|
||||
reg = <0x20>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "SELB", "LVDS_RESET",
|
||||
"LVDS_STBYB", "LVDS_PWM_BL",
|
||||
"LVDS_L/R", "LVDS_U/D",
|
||||
"LVDS_CTP_/RST", "";
|
||||
/*
|
||||
* reset shared between U37 and U48, to be
|
||||
* supported once gpio-pca953x switches to
|
||||
* reset framework.
|
||||
*
|
||||
* reset-gpios = <&tca6416_u21 4
|
||||
* (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>;
|
||||
*/
|
||||
gpio-controller;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&phy0 {
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* LED_0 pin */
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
default-state = "keep";
|
||||
function = LED_FUNCTION_LAN;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
/* UARTA */
|
||||
scif1_pins: scif1 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(40, 1, 1)>, /* SCIF1_RXD */
|
||||
<RZG2L_PORT_PINMUX(40, 0, 1)>; /* SCIF1_TXD */
|
||||
};
|
||||
|
||||
/* UARTB */
|
||||
scif3_pins: scif3 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(0, 1, 5)>, /* SCIF3_RXD */
|
||||
<RZG2L_PORT_PINMUX(0, 0, 5)>; /* SCIF3_TXD */
|
||||
};
|
||||
};
|
||||
|
||||
&scif1 {
|
||||
pinctrl-0 = <&scif1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif3 {
|
||||
pinctrl-0 = <&scif3_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
/* native cs does not support cs persistence required for tpm */
|
||||
cs-gpios = <&pinctrl RZG2L_GPIO(44, 3) GPIO_ACTIVE_LOW>;
|
||||
num-cs = <1>;
|
||||
pinctrl-0 = <&spi1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
spi1_muxed: spi@0 {
|
||||
compatible = "spi-mux";
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
mux-controls = <&spi_mux>;
|
||||
/* mux bandwidth is 2GHz, soc max. spi clock is P0/2 = 50MHz */
|
||||
spi-max-frequency = <50000000>;
|
||||
|
||||
tpm@0 {
|
||||
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
|
||||
reg = <0>;
|
||||
interrupts-extended = <&tca6416_u21 9 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-gpios = <&tca6416_u21 1 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
|
||||
spi-max-frequency = <43000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb2_phy0 {
|
||||
vbus-supply = <&vbus1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Device Tree Overlay for the RZ/G2L(C) Solidrun SOM SD
|
||||
*
|
||||
* Copyright (C) 2024 SolidRun Ltd.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
|
||||
|
||||
&sdhi0 {
|
||||
bus-width = <4>;
|
||||
full-pwr-cycle;
|
||||
mux-states = <&sdhi0_mux 1>;
|
||||
pinctrl-0 = <&sdhi0_4bit_pins>, <&sdhi0_cd_pins>;
|
||||
pinctrl-1 = <&sdhi0_4bit_uhs_pins>, <&sdhi0_cd_pins>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
sd-uhs-sdr104;
|
||||
sd-uhs-sdr50;
|
||||
vmmc-supply = <&vmmc>;
|
||||
vqmmc-supply = <®_pmic_ldo1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,79 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Copyright 2025 Josua Mayer <josua@solid-run.com>
|
||||
*
|
||||
* Overlay for enabling HummingBoard IIoT MIPI-DSI connector
|
||||
* with Winstar WJ70N3TYJHMNG0 panel.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
&{/} {
|
||||
dsi_backlight: dsi-backlight {
|
||||
compatible = "gpio-backlight";
|
||||
gpios = <&tca6408_u48 3 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c_dsi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
touchscreen@41 {
|
||||
compatible = "ilitek,ili2130";
|
||||
reg = <0x41>;
|
||||
/*
|
||||
* Touchscreen fires short active-low pulses which level trigger
|
||||
* on i2c gpio expander can miss. Trigger on falling edge instead.
|
||||
*/
|
||||
interrupts-extended = <&tca6416_u21 13 IRQ_TYPE_EDGE_FALLING>;
|
||||
reset-gpios = <&tca6408_u48 6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&dsi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
panel@0 {
|
||||
/* This is a Winstar panel, but the ronbo panel uses same controls. */
|
||||
compatible = "ronbo,rb070d30";
|
||||
reg = <0>;
|
||||
/* reset is active-low but driver inverts it internally */
|
||||
reset-gpios = <&tca6408_u48 1 GPIO_ACTIVE_HIGH>;
|
||||
backlight = <&dsi_backlight>;
|
||||
power-gpios = <&tca6408_u48 2 GPIO_ACTIVE_HIGH>;
|
||||
shlr-gpios = <&tca6408_u48 4 GPIO_ACTIVE_LOW>;
|
||||
updn-gpios = <&tca6408_u48 5 GPIO_ACTIVE_HIGH>;
|
||||
vcc-lcd-supply = <®_dsi_panel>;
|
||||
|
||||
port {
|
||||
dsi_in_panel: endpoint {
|
||||
remote-endpoint = <&mipi_dsi_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
mipi_dsi_out: endpoint {
|
||||
data-lanes = <1 2 3 4>;
|
||||
remote-endpoint = <&dsi_in_panel>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Copyright 2025 Josua Mayer <josua@solid-run.com>
|
||||
*
|
||||
* Overlay for enabling HummingBoard IIoT on-board RS485 Port A on connector J5004.
|
||||
*
|
||||
* Because Renesas uart driver does not support rs485,
|
||||
* users must manually toggle P41_1 between RX & TX.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
&scif1_rs_232_485_mux {
|
||||
/* select rs485 */
|
||||
idle-state = <1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Copyright 2025 Josua Mayer <josua@solid-run.com>
|
||||
*
|
||||
* Overlay for enabling HummingBoard IIoT on-board RS485 Port B on connector J5004.
|
||||
*
|
||||
* Because Renesas uart driver does not support rs485,
|
||||
* users must manually toggle P41_0 between RX & TX.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
&scif3_rs_232_485_mux {
|
||||
/* select rs485 */
|
||||
idle-state = <1>;
|
||||
};
|
||||
49
arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot.dtsi
Normal file
49
arch/arm64/boot/dts/renesas/rzg2l-hummingboard-iiot.dtsi
Normal file
|
|
@ -0,0 +1,49 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Copyright 2025 Josua Mayer <josua@solid-run.com>
|
||||
*/
|
||||
|
||||
#include "rzg2l-hummingboard-iiot-common.dtsi"
|
||||
|
||||
&canfd {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&can0_pins>, <&can1_pins>;
|
||||
status = "okay";
|
||||
|
||||
channel0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
channel1 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&phy1 {
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* LED_0 pin */
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
/* CANA */
|
||||
can0_pins: can0 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(10, 1, 2)>, /* CAN0_TX */
|
||||
<RZG2L_PORT_PINMUX(11, 0, 2)>; /* CAN0_RX */
|
||||
};
|
||||
|
||||
/* CANB */
|
||||
can1_pins: can1 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(12, 1, 2)>, /* CAN1_TX */
|
||||
<RZG2L_PORT_PINMUX(13, 0, 2)>; /* CAN1_RX */
|
||||
};
|
||||
};
|
||||
116
arch/arm64/boot/dts/renesas/rzg2l-hummingboard-pulse-common.dtsi
Normal file
116
arch/arm64/boot/dts/renesas/rzg2l-hummingboard-pulse-common.dtsi
Normal file
|
|
@ -0,0 +1,116 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Copyright 2025 Josua Mayer <josua@solid-run.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/leds/common.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
rtc0 = &carrier_rtc;
|
||||
rtc1 = &pmic;
|
||||
};
|
||||
|
||||
v_1_2: regulator-1v2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "1v2";
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-min-microvolt = <1200000>;
|
||||
vin-supply = <®_pmic_buck4>;
|
||||
};
|
||||
|
||||
vmmc: regulator-mmc {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmc";
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
startup-delay-us = <250>;
|
||||
vin-supply = <®_pmic_buck4>;
|
||||
};
|
||||
|
||||
vmpcie: regulator-mpcie {
|
||||
/* supplies mpcie and m2 connectors */
|
||||
regulator-name = "vmpcie";
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
&ehci1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
hub_2_0: hub@1 {
|
||||
compatible = "usb4b4,6502", "usb4b4,6506";
|
||||
reg = <1>;
|
||||
vdd2-supply = <®_pmic_buck4>;
|
||||
vdd-supply = <&v_1_2>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
carrier_eeprom: eeprom@57 {
|
||||
compatible = "st,24c02", "atmel,24c02";
|
||||
reg = <0x57>;
|
||||
pagesize = <16>;
|
||||
};
|
||||
|
||||
carrier_rtc: rtc@69 {
|
||||
compatible = "abracon,ab1805";
|
||||
reg = <0x69>;
|
||||
abracon,tc-diode = "schottky";
|
||||
abracon,tc-resistor = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&ohci1 {
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&phy0 {
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
color = <LED_COLOR_ID_ORANGE>;
|
||||
default-state = "keep";
|
||||
function = LED_FUNCTION_LAN;
|
||||
};
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
default-state = "keep";
|
||||
function = LED_FUNCTION_LAN;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* mikrobus uart */
|
||||
&scif1 {
|
||||
pinctrl-0 = <&mikro_uart_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* mikrobus spi */
|
||||
&spi1 {
|
||||
num-cs = <1>;
|
||||
pinctrl-0 = <&spi1_pins>, <&spi1_cs_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy0 {
|
||||
pinctrl-0 = <&usb0_vbus_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
|
@ -0,0 +1,79 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Copyright 2025 Josua Mayer <josua@solid-run.com>
|
||||
*/
|
||||
|
||||
/ {
|
||||
hdmi-connector {
|
||||
compatible = "hdmi-connector";
|
||||
label = "hdmi";
|
||||
type = "d";
|
||||
|
||||
port {
|
||||
hdmi_connector_in: endpoint {
|
||||
remote-endpoint = <&adv7535_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vmipi: regulator-mipi-1-8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmipi";
|
||||
regulator-always-on;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
vin-supply = <®_pmic_buck4>;
|
||||
};
|
||||
};
|
||||
|
||||
&dsi {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
mipi_dsi_out: endpoint {
|
||||
data-lanes = <1 2 3 4>;
|
||||
remote-endpoint = <&adv7535_from_dsim>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
hdmi: hdmi@3d {
|
||||
compatible = "adi,adv7535";
|
||||
reg = <0x3d>, <0x3f>, <0x3c>, <0x38>;
|
||||
reg-names = "main", "edid", "cec", "packet";
|
||||
a2vdd-supply = <&vmipi>;
|
||||
avdd-supply = <&vmipi>;
|
||||
dvdd-supply = <&vmipi>;
|
||||
pvdd-supply = <&vmipi>;
|
||||
v3p3-supply = <®_pmic_buck4>;
|
||||
adi,dsi-lanes = <4>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
adv7535_from_dsim: endpoint {
|
||||
remote-endpoint = <&mipi_dsi_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
adv7535_out: endpoint {
|
||||
remote-endpoint = <&hdmi_connector_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
122
arch/arm64/boot/dts/renesas/rzg2l-hummingboard-ripple.dtsi
Normal file
122
arch/arm64/boot/dts/renesas/rzg2l-hummingboard-ripple.dtsi
Normal file
|
|
@ -0,0 +1,122 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Copyright 2025 Josua Mayer <josua@solid-run.com>
|
||||
*/
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
/* this board does not use second phy / ethernet on SoM */
|
||||
/delete-property/ ethernet1;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led-0 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
default-state = "on";
|
||||
gpios = <&pinctrl RZG2L_GPIO(0, 1) GPIO_ACTIVE_LOW>;
|
||||
label = "D30";
|
||||
};
|
||||
|
||||
led-1 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
default-state = "on";
|
||||
gpios = <&pinctrl RZG2L_GPIO(47, 2) GPIO_ACTIVE_LOW>;
|
||||
label = "D31";
|
||||
};
|
||||
|
||||
led-2 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
default-state = "on";
|
||||
gpios = <&pinctrl RZG2L_GPIO(47, 1) GPIO_ACTIVE_LOW>;
|
||||
label = "D32";
|
||||
};
|
||||
|
||||
led-3 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
default-state = "on";
|
||||
gpios = <&pinctrl RZG2L_GPIO(48, 2) GPIO_ACTIVE_LOW>;
|
||||
label = "D33";
|
||||
};
|
||||
|
||||
led-4 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
default-state = "on";
|
||||
gpios = <&pinctrl RZG2L_GPIO(7, 2) GPIO_ACTIVE_LOW>;
|
||||
label = "D34";
|
||||
};
|
||||
};
|
||||
|
||||
rfkill-mpcie {
|
||||
/* rfkill-gpio inverts internally */
|
||||
shutdown-gpios = <&pinctrl RZG2L_GPIO(14, 1) GPIO_ACTIVE_HIGH>;
|
||||
label = "mpcie radio";
|
||||
/*
|
||||
* The mpcie connector only has USB,
|
||||
* therefore this rfkill is for cellular radios only.
|
||||
*/
|
||||
radio-type = "wwan";
|
||||
compatible = "rfkill-gpio";
|
||||
};
|
||||
};
|
||||
|
||||
ð1 {
|
||||
/* this board does not use second phy / ethernet on SoM */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&gpt {
|
||||
/* mikrobus header pwm pin is pwm channel 6 */
|
||||
pinctrl-0 = <&mikro_pwm_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
interrupts-extended = <&pinctrl RZG2L_GPIO(9, 1) IRQ_TYPE_EDGE_FALLING>;
|
||||
pd-gpios = <&pinctrl RZG2L_GPIO(3, 0) GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&hub_2_0 {
|
||||
reset-gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
mpcie_rst_hog: mpcie-reset-hog {
|
||||
gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_LOW>;
|
||||
gpio-hog;
|
||||
line-name = "mpcie-reset";
|
||||
output-low;
|
||||
};
|
||||
|
||||
mikro_pwm_pins: pinctrl-mikro-pwm-grp {
|
||||
pinmux = <RZG2L_PORT_PINMUX(41, 0, 4)>; /* GTIOC3A */
|
||||
};
|
||||
|
||||
mikro_uart_pins: pinctrl-mikro-uart-grp {
|
||||
pinmux = <RZG2L_PORT_PINMUX(40, 1, 1)>, /* SCIF1_RXD */
|
||||
<RZG2L_PORT_PINMUX(40, 0, 1)>; /* SCIF1_TXD */
|
||||
};
|
||||
|
||||
usb0_vbus_pins: usb0-vbus {
|
||||
pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>; /* USB0_VBUSEN */
|
||||
};
|
||||
|
||||
usb1_vbus_pins: usb1-vbus {
|
||||
pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>; /* USB1_VBUSEN */
|
||||
};
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
pinctrl-0 = <&usb1_vbus_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&vmmc {
|
||||
gpios = <&pinctrl RZG2L_GPIO(4, 1) GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&vmpcie {
|
||||
gpios = <&pinctrl RZG2L_GPIO(17, 0) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
44
arch/arm64/boot/dts/renesas/rzg2l-sr-som-emmc.dtso
Normal file
44
arch/arm64/boot/dts/renesas/rzg2l-sr-som-emmc.dtso
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Device Tree Overlay for the RZ/G2L(C) Solidrun SOM eMMC
|
||||
*
|
||||
* Copyright (C) 2024 SolidRun Ltd.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
|
||||
|
||||
®_pmic_ldo1 {
|
||||
/*
|
||||
* This ldo can switch mmc host controller io voltage between
|
||||
* 1.8V and 3.3V. The eMMC IO voltage however is supplied from
|
||||
* reg_pmic_buck3 which is fixed at 1.8V.
|
||||
* Lower this ldo maximum voltage to 1.8V to prevent setting 3.3V.
|
||||
*/
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
/*
|
||||
* Host controller and eMMC have separate io voltage regulators:
|
||||
* reg_pmic_ldo1 (1.8V/3.3V); reg_pmic_buck3 (1.8V only).
|
||||
* Link to the switchable regulator ensuring that it gets configured.
|
||||
*/
|
||||
vqmmc-supply = <®_pmic_ldo1>;
|
||||
bus-width = <8>;
|
||||
cap-mmc-hw-reset;
|
||||
mmc-hs200-1_8v;
|
||||
mux-states = <&sdhi0_mux 0>;
|
||||
non-removable;
|
||||
no-sdio;
|
||||
pinctrl-0 = <&sdhi0_8bit_uhs_pins>, <&sdhi0_rst_pins>;
|
||||
pinctrl-1 = <&sdhi0_8bit_uhs_pins>, <&sdhi0_rst_pins>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
vmmc-supply = <®_pmic_buck4>;
|
||||
/* emmc io voltage is hard-wired for 1.8V, disable sd modes */
|
||||
no-sd;
|
||||
status = "okay";
|
||||
};
|
||||
473
arch/arm64/boot/dts/renesas/rzg2l-sr-som.dtsi
Normal file
473
arch/arm64/boot/dts/renesas/rzg2l-sr-som.dtsi
Normal file
|
|
@ -0,0 +1,473 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Device Tree Source for the RZ/G2L Solidrun SoM
|
||||
*
|
||||
* Copyright 2023 SolidRun Ltd.
|
||||
* Copyright 2025 Josua Mayer <josua@solid-run.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
ethernet0 = ð0;
|
||||
ethernet1 = ð1;
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c3;
|
||||
mmc0 = &sdhi0;
|
||||
mmc1 = &sdhi1;
|
||||
rtc0 = &pmic;
|
||||
serial0 = &scif0;
|
||||
serial1 = &scif1;
|
||||
serial2 = &scif2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@48000000 {
|
||||
/*
|
||||
* Physical RAM starts at 0x40000000, but Renesas RZ/G2 BSPs
|
||||
* reserve and hide the first 128MB for TrustZone by default.
|
||||
*
|
||||
* Minimum size for this SoM is 1GB, and the bootloader patches
|
||||
* the dtb according to the actual RAM size and reservations.
|
||||
*/
|
||||
reg = <0x0 0x48000000 0x0 0x38000000>;
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
sdhi0_mux: mux-controller-0 {
|
||||
compatible = "gpio-mux";
|
||||
#mux-control-cells = <0>;
|
||||
#mux-state-cells = <1>;
|
||||
/*
|
||||
* Mux switches SD0_DATA[0-3], SD0_CMD & SD0_CLK between
|
||||
* on-SoM eMMC and board-to-board connector using one gpio:
|
||||
* Low = connector, High = eMMC.
|
||||
* Define active-low for logical mux state 0 = eMMC, 1 = connector.
|
||||
*/
|
||||
mux-gpios = <&pinctrl RZG2L_GPIO(22, 1) GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
reg_pmic_buck1: regulator-pmic-buck1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pmic-buck1";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-min-microvolt = <1100000>;
|
||||
};
|
||||
|
||||
reg_pmic_buck3: regulator-pmic-buck3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pmic-buck3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
reg_pmic_buck4: regulator-pmic-buck4 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pmic-buck4";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
reg_pmic_ldo1: regulator-pmic-ldo1 {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "pmic-ldo1";
|
||||
gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
states = <3300000 1>, <1800000 0>;
|
||||
};
|
||||
|
||||
reg_pmic_ldo2: regulator-pmic-ldo2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pmic-ldo2";
|
||||
/*
|
||||
* This ldo can switch mmc host controller io voltage between
|
||||
* 1.8V and 3.3V by assembly option of pull-up / pull-dow.
|
||||
* Default assembly is 3.3V.
|
||||
*/
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
ranges;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
global_cma: linux,cma@58000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x0 0x58000000 0x0 0x10000000>;
|
||||
reusable;
|
||||
linux,cma-default;
|
||||
};
|
||||
};
|
||||
|
||||
sdhi1_pwrseq: sdhi1-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
reset-gpios = <&pinctrl RZG2L_GPIO(23, 1) GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
/* 32.768kHz crystal */
|
||||
x2: x2-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ð0 {
|
||||
phy-handle = <&phy0>;
|
||||
pinctrl-0 = <ð0_pins>;
|
||||
pinctrl-names = "default";
|
||||
/*
|
||||
* ravb driver does not configure mac internal delays for RZ/G2L(C),
|
||||
* instead delays are added by the MxL86110 phy driver.
|
||||
*/
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
/* Level interrupts are typical for phy but not supported on RZ/G2L gpios. */
|
||||
interrupts-extended = <&pinctrl RZG2L_GPIO(27, 0) IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
};
|
||||
|
||||
ð1 {
|
||||
phy-handle = <&phy1>;
|
||||
pinctrl-0 = <ð1_pins>;
|
||||
pinctrl-names = "default";
|
||||
/*
|
||||
* ravb driver does not configure mac internal delays for RZ/G2L(C),
|
||||
* instead delays are added by the MxL86110 phy driver.
|
||||
*/
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@4 {
|
||||
reg = <4>;
|
||||
/* Level interrupts are typical for phy but not supported on RZ/G2L gpios. */
|
||||
interrupts-extended = <&pinctrl RZG2L_GPIO(42, 4) IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <®_pmic_buck1>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
eeprom: eeprom@50 {
|
||||
compatible = "atmel,24c01";
|
||||
reg = <0x50>;
|
||||
pagesize = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-0 = <&i2c3_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
pmic: pmic@12 {
|
||||
compatible = "renesas,raa215300";
|
||||
reg = <0x12>, <0x6f>;
|
||||
reg-names = "main", "rtc";
|
||||
clocks = <&x2>;
|
||||
clock-names = "xin";
|
||||
};
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ostm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ostm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&phyrst {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
eth0_pins: eth0 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
|
||||
<RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
|
||||
<RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
|
||||
<RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
|
||||
<RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
|
||||
<RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
|
||||
<RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
|
||||
<RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
|
||||
<RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
|
||||
<RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
|
||||
<RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
|
||||
<RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
|
||||
<RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
|
||||
<RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
|
||||
<RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
|
||||
};
|
||||
|
||||
eth1_pins: eth1 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */
|
||||
<RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
|
||||
<RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
|
||||
<RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
|
||||
<RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
|
||||
<RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
|
||||
<RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
|
||||
<RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
|
||||
<RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
|
||||
<RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
|
||||
<RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
|
||||
<RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
|
||||
<RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
|
||||
<RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
|
||||
<RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0 {
|
||||
input-enable;
|
||||
pins = "RIIC0_SDA", "RIIC0_SCL";
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1 {
|
||||
input-enable;
|
||||
pins = "RIIC1_SDA", "RIIC1_SCL";
|
||||
};
|
||||
|
||||
i2c3_pins: i2c3 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* RIIC3_SDA */
|
||||
<RZG2L_PORT_PINMUX(18, 1, 3)>; /* RIIC3_SCL */
|
||||
};
|
||||
|
||||
qspi0_pins: qspi0 {
|
||||
pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3",
|
||||
"QSPI0_SPCLK", "QSPI0_SSL";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
scif0_pins: scif0 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* SCIF0_TXD */
|
||||
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* SCIF0_RXD */
|
||||
};
|
||||
|
||||
scif2_pins: scif2 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(48, 0, 1)>, /* SCIF2_TXD */
|
||||
<RZG2L_PORT_PINMUX(48, 1, 1)>, /* SCIF2_RXD */
|
||||
<RZG2L_PORT_PINMUX(48, 3, 1)>, /* SCIF2_CTS# */
|
||||
<RZG2L_PORT_PINMUX(48, 4, 1)>; /* SCIF2_RTS# */
|
||||
};
|
||||
|
||||
sdhi0_4bit_pins: sdhi0-4bit {
|
||||
sd0-ctrl-dat03 {
|
||||
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
|
||||
"SD0_CLK", "SD0_CMD";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Pins 4-7 are hard-wired to eMMC with 1.8V IO voltage,
|
||||
* with all pins sharing a single voltage domain.
|
||||
*
|
||||
* These pins are fixed-function lacking independently configurable
|
||||
* pull-up, pull-down or output-disable.
|
||||
*
|
||||
* While unused, disable the input buffers to avoid sampling the still
|
||||
* physically connected but unused eMMC lines.
|
||||
* For output direction rely on correct controller bus-width configuration
|
||||
* to avoid over-voltage to eMMC e.g. when operating at 3.3V for a 4-bit microSD.
|
||||
*/
|
||||
sd0-dat47 {
|
||||
input-disable;
|
||||
pins = "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
|
||||
};
|
||||
};
|
||||
|
||||
sdhi0_4bit_uhs_pins: sdhi0-4bit-uhs {
|
||||
sd0-ctrl-dat03 {
|
||||
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
|
||||
"SD0_CLK", "SD0_CMD";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Pins 4-7 are hard-wired to eMMC with 1.8V IO voltage,
|
||||
* with all pins sharing a single voltage domain.
|
||||
*
|
||||
* These pins are fixed-function, lacking configurable pull-up, pull-down or
|
||||
* output-disable, while sharing the voltage domain with all SD0_* pins.
|
||||
*
|
||||
* While unused, disable the input buffers to avoid sampling the still
|
||||
* physically connected but unused eMMC lines.
|
||||
* For output direction rely on correct controller bus-width configuration
|
||||
* to avoid over-voltage to eMMC e.g. when operating at 3.3V for a 4-bit microSD.
|
||||
*/
|
||||
sd0-dat47 {
|
||||
input-disable;
|
||||
pins = "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
|
||||
};
|
||||
};
|
||||
|
||||
sdhi0_8bit_uhs_pins: sdhi0-8bit-uhs {
|
||||
sd0-ctrl {
|
||||
pins = "SD0_CLK", "SD0_CMD";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sd0-dat {
|
||||
input-enable;
|
||||
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
|
||||
"SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
|
||||
};
|
||||
};
|
||||
|
||||
sdhi0_cd_pins: sdhi0-cd {
|
||||
pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
|
||||
};
|
||||
|
||||
/* SD0_RST is only routed to eMMC which uses fixed 1.8V IO voltage */
|
||||
sdhi0_rst_pins: sdhi0-rst {
|
||||
pins = "SD0_RST#";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi1_pins: sdhi1 {
|
||||
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3",
|
||||
"SD1_CLK", "SD1_CMD";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
spi1_pins: spi1 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(44, 2, 1)>, /* RSPI1_MISO */
|
||||
<RZG2L_PORT_PINMUX(44, 1, 1)>, /* RSPI1_MOSI */
|
||||
<RZG2L_PORT_PINMUX(44, 0, 1)>; /* RSPI1_CK */
|
||||
};
|
||||
|
||||
spi1_cs_pins: spi1-cs {
|
||||
pinmux = <RZG2L_PORT_PINMUX(44, 3, 1)>; /* RSPI1_SSL */
|
||||
};
|
||||
};
|
||||
|
||||
&sbc {
|
||||
pinctrl-0 = <&qspi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "winbond,w25q80bl", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <50000000>;
|
||||
m25p,fast-read;
|
||||
};
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif2 {
|
||||
pinctrl-0 = <&scif2_pins>;
|
||||
pinctrl-names = "default";
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
|
||||
bluetooth {
|
||||
/*
|
||||
* The BT is based on BCM4345C0. Murata 1MW variant seems to
|
||||
* require driving RTS on open.
|
||||
* Use compatible bcm43438 to accomplish this.
|
||||
*/
|
||||
compatible = "brcm,bcm43438-bt";
|
||||
max-speed = <115200>;
|
||||
shutdown-gpios = <&pinctrl RZG2L_GPIO(23, 0) GPIO_ACTIVE_HIGH>;
|
||||
vbat-supply = <®_pmic_buck4>;
|
||||
vddio-supply = <®_pmic_buck4>;
|
||||
};
|
||||
};
|
||||
|
||||
/* WiFi */
|
||||
&sdhi1 {
|
||||
/* Murata 1MW max rate is 50MHz */
|
||||
max-frequency = <50000000>;
|
||||
bus-width = <4>;
|
||||
cap-sdio-irq;
|
||||
mmc-pwrseq = <&sdhi1_pwrseq>;
|
||||
non-removable;
|
||||
no-1-8-v;
|
||||
no-sd;
|
||||
pinctrl-0 = <&sdhi1_pins>;
|
||||
pinctrl-names = "default";
|
||||
vmmc-supply = <®_pmic_buck4>;
|
||||
/*
|
||||
* Host controller IO voltage is provided from reg_pmic_ldo2,
|
||||
* WiFi module IO voltage from reg_pmic_buck4.
|
||||
* Neither is configurable at run-time so either can be set here.
|
||||
*/
|
||||
vqmmc-supply = <®_pmic_ldo2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy0 {
|
||||
vbus-supply = <&usb0_vbus_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdt0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Overlay for SolidRun RZ/G2LC HummingBoard Pulse
|
||||
* enabling LEDs D31-34 in exchange for on-SoM Bluetooth.
|
||||
*
|
||||
* Copyright 2025 Josua Mayer <josua@solid-run.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
|
||||
|
||||
&leds {
|
||||
led-1 {
|
||||
label = "D31";
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
gpios = <&pinctrl RZG2L_GPIO(5, 2) GPIO_ACTIVE_LOW>;
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
led-2 {
|
||||
label = "D32";
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
gpios = <&pinctrl RZG2L_GPIO(5, 1) GPIO_ACTIVE_LOW>;
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
led-3 {
|
||||
label = "D33";
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
gpios = <&pinctrl RZG2L_GPIO(42, 0) GPIO_ACTIVE_LOW>;
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
led-4 {
|
||||
label = "D34";
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
gpios = <&pinctrl RZG2L_GPIO(42, 1) GPIO_ACTIVE_LOW>;
|
||||
default-state = "on";
|
||||
};
|
||||
};
|
||||
|
||||
&scif2 {
|
||||
status = "disabled";
|
||||
};
|
||||
436
arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi
Normal file
436
arch/arm64/boot/dts/renesas/rzg2lc-sr-som.dtsi
Normal file
|
|
@ -0,0 +1,436 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Device Tree Source for the RZ/G2LC Solidrun SOM
|
||||
*
|
||||
* Copyright 2023 SolidRun Ltd.
|
||||
* Copyright 2025 Josua Mayer <josua@solid-run.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
ethernet0 = ð0;
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
mmc0 = &sdhi0;
|
||||
mmc1 = &sdhi1;
|
||||
rtc0 = &pmic;
|
||||
serial0 = &scif0;
|
||||
serial1 = &scif1;
|
||||
serial2 = &scif2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@48000000 {
|
||||
/*
|
||||
* Physical RAM starts at 0x40000000, but Renesas RZ/G2 BSPs
|
||||
* reserve and hide the first 128MB for TrustZone by default.
|
||||
*
|
||||
* Minimum size for this SoM is 1GB, and the bootloader patches
|
||||
* the dtb according to the actual RAM size and reservations.
|
||||
*/
|
||||
reg = <0x0 0x48000000 0x0 0x38000000>;
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
sdhi0_mux: mux-controller-0 {
|
||||
compatible = "gpio-mux";
|
||||
#mux-control-cells = <0>;
|
||||
#mux-state-cells = <1>;
|
||||
/*
|
||||
* Mux switches SD0_DATA[0-3], SD0_CMD & SD0_CLK between
|
||||
* on-SoM eMMC and board-to-board connector using one gpio:
|
||||
* High = connector, Low = eMMC.
|
||||
* Define active-high for logical mux state 0 = eMMC, 1 = connector.
|
||||
*/
|
||||
mux-gpios = <&pinctrl RZG2L_GPIO(22, 1) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_pmic_buck1: regulator-pmic-buck1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pmic-buck1";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-min-microvolt = <1100000>;
|
||||
};
|
||||
|
||||
reg_pmic_buck3: regulator-pmic-buck3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pmic-buck3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
reg_pmic_buck4: regulator-pmic-buck4 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pmic-buck4";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
reg_pmic_ldo1: regulator-pmic-ldo1 {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "pmic-ldo1";
|
||||
gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
states = <3300000 1>, <1800000 0>;
|
||||
};
|
||||
|
||||
reg_pmic_ldo2: regulator-pmic-ldo2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pmic-ldo2";
|
||||
/*
|
||||
* This ldo can switch mmc host controller io voltage between
|
||||
* 1.8V and 3.3V by assembly option of pull-up / pull-dow.
|
||||
* Default assembly is 3.3V.
|
||||
*/
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
ranges;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
global_cma: linux,cma@58000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x0 0x58000000 0x0 0x10000000>;
|
||||
reusable;
|
||||
linux,cma-default;
|
||||
};
|
||||
};
|
||||
|
||||
sdhi1_pwrseq: sdhi1-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
reset-gpios = <&pinctrl RZG2L_GPIO(23, 0) GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
/* 32.768kHz crystal */
|
||||
x2: x2-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ð0 {
|
||||
phy-handle = <&phy0>;
|
||||
pinctrl-0 = <ð0_pins>;
|
||||
pinctrl-names = "default";
|
||||
/*
|
||||
* ravb driver does not configure mac internal delays for RZ/G2L(C),
|
||||
* instead delays are added by the ADIN1200 phy driver.
|
||||
*/
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
/* Level interrupts are typical for phy but not supported on RZ/G2L gpios. */
|
||||
interrupts-extended = <&pinctrl RZG2L_GPIO(27, 0) IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <®_pmic_buck1>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
eeprom: eeprom@50 {
|
||||
compatible = "atmel,24c01";
|
||||
reg = <0x50>;
|
||||
pagesize = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
pmic: pmic@12 {
|
||||
compatible = "renesas,raa215300";
|
||||
reg = <0x12>, <0x6f>;
|
||||
reg-names = "main", "rtc";
|
||||
clocks = <&x2>;
|
||||
clock-names = "xin";
|
||||
};
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ostm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ostm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&phyrst {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
eth0_pins: eth0 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
|
||||
<RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
|
||||
<RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
|
||||
<RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
|
||||
<RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
|
||||
<RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
|
||||
<RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
|
||||
<RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
|
||||
<RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
|
||||
<RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
|
||||
<RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
|
||||
<RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
|
||||
<RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
|
||||
<RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
|
||||
<RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0 {
|
||||
input-enable;
|
||||
pins = "RIIC0_SDA", "RIIC0_SCL";
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1 {
|
||||
input-enable;
|
||||
pins = "RIIC1_SDA", "RIIC1_SCL";
|
||||
};
|
||||
|
||||
i2c2_pins: i2c2 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(42, 3, 1)>, /* RIIC2_SDA */
|
||||
<RZG2L_PORT_PINMUX(42, 4, 1)>; /* RIIC2_SCL */
|
||||
};
|
||||
|
||||
qspi0_pins: qspi0 {
|
||||
pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3",
|
||||
"QSPI0_SPCLK", "QSPI0_SSL";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
scif0_pins: scif0 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* SCIF0_TXD */
|
||||
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* SCIF0_RXD */
|
||||
};
|
||||
|
||||
scif2_pins: scif2 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(42, 0, 4)>, /* SCIF2_TXD */
|
||||
<RZG2L_PORT_PINMUX(42, 1, 4)>, /* SCIF2_RXD */
|
||||
<RZG2L_PORT_PINMUX(5, 1, 2)>, /* SCIF2_CTS# */
|
||||
<RZG2L_PORT_PINMUX(5, 2, 2)>; /* SCIF2_RTS# */
|
||||
};
|
||||
|
||||
sdhi0_4bit_pins: sdhi0-4bit {
|
||||
sd0-ctrl-dat03 {
|
||||
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
|
||||
"SD0_CLK", "SD0_CMD";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Pins 4-7 are hard-wired to eMMC with 1.8V IO voltage,
|
||||
* with all pins sharing a single voltage domain.
|
||||
*
|
||||
* These pins are fixed-function lacking independently configurable
|
||||
* pull-up, pull-down or output-disable.
|
||||
*
|
||||
* While unused, disable the input buffers to avoid sampling the still
|
||||
* physically connected but unused eMMC lines.
|
||||
* For output direction rely on correct controller bus-width configuration
|
||||
* to avoid over-voltage to eMMC e.g. when operating at 3.3V for a 4-bit microSD.
|
||||
*/
|
||||
sd0-dat47 {
|
||||
input-disable;
|
||||
pins = "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
|
||||
};
|
||||
};
|
||||
|
||||
sdhi0_4bit_uhs_pins: sdhi0-4bit-uhs {
|
||||
sd0-ctrl-dat03 {
|
||||
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
|
||||
"SD0_CLK", "SD0_CMD";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Pins 4-7 are hard-wired to eMMC with 1.8V IO voltage,
|
||||
* with all pins sharing a single voltage domain.
|
||||
*
|
||||
* These pins are fixed-function, lacking configurable pull-up, pull-down or
|
||||
* output-disable, while sharing the voltage domain with all SD0_* pins.
|
||||
*
|
||||
* While unused, disable the input buffers to avoid sampling the still
|
||||
* physically connected but unused eMMC lines.
|
||||
* For output direction rely on correct controller bus-width configuration
|
||||
* to avoid over-voltage to eMMC e.g. when operating at 3.3V for a 4-bit microSD.
|
||||
*/
|
||||
sd0-dat47 {
|
||||
input-disable;
|
||||
pins = "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
|
||||
};
|
||||
};
|
||||
|
||||
sdhi0_8bit_uhs_pins: sdhi0-8bit-uhs {
|
||||
sd0-ctrl {
|
||||
pins = "SD0_CLK", "SD0_CMD";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sd0-dat {
|
||||
input-enable;
|
||||
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
|
||||
"SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
|
||||
};
|
||||
};
|
||||
|
||||
sdhi0_cd_pins: sdhi0-cd {
|
||||
pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */
|
||||
};
|
||||
|
||||
/* SD0_RST is only routed to eMMC which uses fixed 1.8V IO voltage */
|
||||
sdhi0_rst_pins: sdhi0-rst {
|
||||
pins = "SD0_RST#";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi1_pins: sdhi1 {
|
||||
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3",
|
||||
"SD1_CLK", "SD1_CMD";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
spi1_pins: spi1 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(44, 2, 1)>, /* RSPI1_MISO */
|
||||
<RZG2L_PORT_PINMUX(44, 1, 1)>, /* RSPI1_MOSI */
|
||||
<RZG2L_PORT_PINMUX(44, 0, 1)>; /* RSPI1_CK */
|
||||
};
|
||||
|
||||
spi1_cs_pins: spi1-cs {
|
||||
pinmux = <RZG2L_PORT_PINMUX(44, 3, 1)>; /* RSPI1_SSL */
|
||||
};
|
||||
};
|
||||
|
||||
&sbc {
|
||||
pinctrl-0 = <&qspi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "winbond,w25q80bl", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <50000000>;
|
||||
m25p,fast-read;
|
||||
};
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif2 {
|
||||
pinctrl-0 = <&scif2_pins>;
|
||||
pinctrl-names = "default";
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
|
||||
bluetooth {
|
||||
/*
|
||||
* The BT is based on BCM4343A2. Murata 1YN variant seems to
|
||||
* require driving RTS on open.
|
||||
* Use compatible bcm43438 to accomplish this.
|
||||
*/
|
||||
compatible = "brcm,bcm43438-bt";
|
||||
max-speed = <115200>;
|
||||
shutdown-gpios = <&pinctrl RZG2L_GPIO(23, 1) GPIO_ACTIVE_HIGH>;
|
||||
vbat-supply = <®_pmic_buck4>;
|
||||
vddio-supply = <®_pmic_buck4>;
|
||||
};
|
||||
};
|
||||
|
||||
/* WiFi */
|
||||
&sdhi1 {
|
||||
/* Murata 1YN max rate is 50MHz */
|
||||
max-frequency = <50000000>;
|
||||
bus-width = <4>;
|
||||
cap-sdio-irq;
|
||||
mmc-pwrseq = <&sdhi1_pwrseq>;
|
||||
non-removable;
|
||||
no-1-8-v;
|
||||
no-sd;
|
||||
pinctrl-0 = <&sdhi1_pins>;
|
||||
pinctrl-names = "default";
|
||||
vmmc-supply = <®_pmic_buck4>;
|
||||
/*
|
||||
* Host controller IO voltage is provided from reg_pmic_ldo2,
|
||||
* WiFi module IO voltage from reg_pmic_buck4.
|
||||
* Neither is configurable at run-time so either can be set here.
|
||||
*/
|
||||
vqmmc-supply = <®_pmic_ldo2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy0 {
|
||||
vbus-supply = <&usb0_vbus_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdt0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Overlay for SolidRun RZ/G2UL HummingBoard Pulse
|
||||
* enabling LEDs D31-34 in exchange for on-SoM Bluetooth.
|
||||
*
|
||||
* Copyright 2025 Josua Mayer <josua@solid-run.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
|
||||
|
||||
&leds {
|
||||
led-1 {
|
||||
label = "D31";
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
gpios = <&pinctrl RZG2L_GPIO(5, 4) GPIO_ACTIVE_LOW>;
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
led-2 {
|
||||
label = "D32";
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
gpios = <&pinctrl RZG2L_GPIO(5, 3) GPIO_ACTIVE_LOW>;
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
led-3 {
|
||||
label = "D33";
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
gpios = <&pinctrl RZG2L_GPIO(6, 0) GPIO_ACTIVE_LOW>;
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
led-4 {
|
||||
label = "D34";
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
gpios = <&pinctrl RZG2L_GPIO(6, 1) GPIO_ACTIVE_LOW>;
|
||||
default-state = "on";
|
||||
};
|
||||
};
|
||||
|
||||
&scif2 {
|
||||
status = "disabled";
|
||||
};
|
||||
418
arch/arm64/boot/dts/renesas/rzg2ul-sr-som.dtsi
Normal file
418
arch/arm64/boot/dts/renesas/rzg2ul-sr-som.dtsi
Normal file
|
|
@ -0,0 +1,418 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/*
|
||||
* Device Tree Source for the RZ/G2UL Solidrun SOM
|
||||
*
|
||||
* Copyright 2025 Josua Mayer <josua@solid-run.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
ethernet0 = ð0;
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
mmc0 = &sdhi0;
|
||||
mmc1 = &sdhi1;
|
||||
rtc0 = &pmic;
|
||||
serial0 = &scif0;
|
||||
serial1 = &scif1;
|
||||
serial2 = &scif2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@48000000 {
|
||||
/*
|
||||
* Physical RAM starts at 0x40000000, but Renesas RZ/G2 BSPs
|
||||
* reserve and hide the first 128MB for TrustZone by default.
|
||||
*
|
||||
* Minimum size for this SoM is 512MB, and the bootloader patches
|
||||
* the dtb according to the actual RAM size and reservations.
|
||||
*/
|
||||
reg = <0x0 0x48000000 0x0 0x18000000>;
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
sdhi0_mux: mux-controller-0 {
|
||||
compatible = "gpio-mux";
|
||||
#mux-control-cells = <0>;
|
||||
#mux-state-cells = <1>;
|
||||
/*
|
||||
* Mux switches SD0_DATA[0-3], SD0_CMD & SD0_CLK between
|
||||
* on-SoM eMMC and board-to-board connector using one gpio:
|
||||
* High = connector, Low = eMMC.
|
||||
* Define active-high for logical mux state 0 = eMMC, 1 = connector.
|
||||
*/
|
||||
mux-gpios = <&pinctrl RZG2L_GPIO(2, 1) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_pmic_buck1: regulator-pmic-buck1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pmic-buck1";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-min-microvolt = <1100000>;
|
||||
};
|
||||
|
||||
reg_pmic_buck3: regulator-pmic-buck3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pmic-buck3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
reg_pmic_buck4: regulator-pmic-buck4 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pmic-buck4";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
reg_pmic_ldo1: regulator-pmic-ldo1 {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "pmic-ldo1";
|
||||
gpios = <&pinctrl RZG2L_GPIO(13, 2) GPIO_ACTIVE_HIGH>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
states = <3300000 1>, <1800000 0>;
|
||||
};
|
||||
|
||||
reg_pmic_ldo2: regulator-pmic-ldo2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pmic-ldo2";
|
||||
/*
|
||||
* This ldo can switch mmc host controller io voltage between
|
||||
* 1.8V and 3.3V by assembly option of pull-up / pull-dow.
|
||||
* Default assembly is 3.3V.
|
||||
*/
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
sdhi1_pwrseq: sdhi1-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
reset-gpios = <&pinctrl RZG2L_GPIO(2, 2) GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
/* 32.768kHz crystal */
|
||||
x2: x2-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ð0 {
|
||||
phy-handle = <&phy0>;
|
||||
pinctrl-0 = <ð0_pins>;
|
||||
pinctrl-names = "default";
|
||||
/*
|
||||
* ravb driver does not configure mac internal delays for RZ/G2(UL/L/C),
|
||||
* instead delays are added by the ADIN1200 phy driver.
|
||||
*/
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
/* Level interrupts are typical for phy but not supported on rz/g2l gpios. */
|
||||
interrupts-extended = <&pinctrl RZG2L_GPIO(4, 2) IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
eeprom: eeprom@50 {
|
||||
compatible = "atmel,24c01";
|
||||
reg = <0x50>;
|
||||
pagesize = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
pmic: pmic@12 {
|
||||
compatible = "renesas,raa215300";
|
||||
reg = <0x12>, <0x6f>;
|
||||
reg-names = "main", "rtc";
|
||||
clocks = <&x2>;
|
||||
clock-names = "xin";
|
||||
};
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ostm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ostm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&phyrst {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
eth0_pins: eth0 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(4, 5, 1)>, /* ET0_LINKSTA */
|
||||
<RZG2L_PORT_PINMUX(4, 3, 1)>, /* ET0_MDC */
|
||||
<RZG2L_PORT_PINMUX(4, 4, 1)>, /* ET0_MDIO */
|
||||
<RZG2L_PORT_PINMUX(1, 0, 1)>, /* ET0_TXC */
|
||||
<RZG2L_PORT_PINMUX(1, 1, 1)>, /* ET0_TX_CTL */
|
||||
<RZG2L_PORT_PINMUX(1, 2, 1)>, /* ET0_TXD0 */
|
||||
<RZG2L_PORT_PINMUX(1, 3, 1)>, /* ET0_TXD1 */
|
||||
<RZG2L_PORT_PINMUX(1, 4, 1)>, /* ET0_TXD2 */
|
||||
<RZG2L_PORT_PINMUX(2, 0, 1)>, /* ET0_TXD3 */
|
||||
<RZG2L_PORT_PINMUX(3, 0, 1)>, /* ET0_RXC */
|
||||
<RZG2L_PORT_PINMUX(3, 1, 1)>, /* ET0_RX_CTL */
|
||||
<RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */
|
||||
<RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */
|
||||
<RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */
|
||||
<RZG2L_PORT_PINMUX(4, 1, 1)>; /* ET0_RXD3 */
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0 {
|
||||
input-enable;
|
||||
pins = "RIIC0_SDA", "RIIC0_SCL";
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1 {
|
||||
input-enable;
|
||||
pins = "RIIC1_SDA", "RIIC1_SCL";
|
||||
};
|
||||
|
||||
i2c2_pins: i2c2 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(6, 3, 1)>, /* RIIC2_SDA */
|
||||
<RZG2L_PORT_PINMUX(6, 4, 1)>; /* RIIC2_SCL */
|
||||
};
|
||||
|
||||
qspi0_pins: qspi0 {
|
||||
pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3",
|
||||
"QSPI0_SPCLK", "QSPI0_SSL";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
scif0_pins: scif0 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(13, 0, 1)>, /* SCIF0_TXD */
|
||||
<RZG2L_PORT_PINMUX(13, 1, 1)>; /* SCIF0_RXD */
|
||||
};
|
||||
|
||||
scif2_pins: scif2 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(6, 0, 4)>, /* SCIF2_TXD */
|
||||
<RZG2L_PORT_PINMUX(6, 1, 4)>, /* SCIF2_RXD */
|
||||
<RZG2L_PORT_PINMUX(5, 3, 2)>, /* SCIF2_CTS# */
|
||||
<RZG2L_PORT_PINMUX(5, 4, 2)>; /* SCIF2_RTS# */
|
||||
};
|
||||
|
||||
sdhi0_4bit_pins: sdhi0-4bit {
|
||||
sd0-ctrl-dat03 {
|
||||
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
|
||||
"SD0_CLK", "SD0_CMD";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Pins 4-7 are hard-wired to eMMC with 1.8V IO voltage,
|
||||
* with all pins sharing a single voltage domain.
|
||||
*
|
||||
* These pins are fixed-function lacking independently configurable
|
||||
* pull-up, pull-down or output-disable.
|
||||
*
|
||||
* While unused, disable the input buffers to avoid sampling the still
|
||||
* physically connected but unused eMMC lines.
|
||||
* For output direction rely on correct controller bus-width configuration
|
||||
* to avoid over-voltage to eMMC e.g. when operating at 3.3V for a 4-bit microSD.
|
||||
*/
|
||||
sd0-dat47 {
|
||||
input-disable;
|
||||
pins = "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
|
||||
};
|
||||
};
|
||||
|
||||
sdhi0_4bit_uhs_pins: sdhi0-4bit-uhs {
|
||||
sd0-ctrl-dat03 {
|
||||
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
|
||||
"SD0_CLK", "SD0_CMD";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Pins 4-7 are hard-wired to eMMC with 1.8V IO voltage,
|
||||
* with all pins sharing a single voltage domain.
|
||||
*
|
||||
* These pins are fixed-function, lacking configurable pull-up, pull-down or
|
||||
* output-disable, while sharing the voltage domain with all SD0_* pins.
|
||||
*
|
||||
* While unused, disable the input buffers to avoid sampling the still
|
||||
* physically connected but unused eMMC lines.
|
||||
* For output direction rely on correct controller bus-width configuration
|
||||
* to avoid over-voltage to eMMC e.g. when operating at 3.3V for a 4-bit microSD.
|
||||
*/
|
||||
sd0-dat47 {
|
||||
input-disable;
|
||||
pins = "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
|
||||
};
|
||||
};
|
||||
|
||||
sdhi0_8bit_uhs_pins: sdhi0-8bit-uhs {
|
||||
sd0-ctrl {
|
||||
pins = "SD0_CLK", "SD0_CMD";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sd0-dat {
|
||||
input-enable;
|
||||
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
|
||||
"SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
|
||||
};
|
||||
};
|
||||
|
||||
sdhi0_cd_pins: sdhi0-cd {
|
||||
pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
|
||||
};
|
||||
|
||||
/* SD0_RST is only routed to eMMC which uses fixed 1.8V IO voltage */
|
||||
sdhi0_rst_pins: sdhi0-rst {
|
||||
pins = "SD0_RST#";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi1_pins: sdhi1 {
|
||||
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3",
|
||||
"SD1_CLK", "SD1_CMD";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
spi1_pins: spi1 {
|
||||
pinmux = <RZG2L_PORT_PINMUX(17, 2, 1)>, /* RSPI1_MISO */
|
||||
<RZG2L_PORT_PINMUX(17, 1, 1)>, /* RSPI1_MOSI */
|
||||
<RZG2L_PORT_PINMUX(17, 0, 1)>; /* RSPI1_CK */
|
||||
};
|
||||
|
||||
spi1_cs_pins: spi1-cs {
|
||||
pinmux = <RZG2L_PORT_PINMUX(17, 3, 1)>; /* RSPI1_SSL */
|
||||
};
|
||||
};
|
||||
|
||||
&sbc {
|
||||
pinctrl-0 = <&qspi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "winbond,w25q80bl", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <50000000>;
|
||||
m25p,fast-read;
|
||||
};
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif2 {
|
||||
pinctrl-0 = <&scif2_pins>;
|
||||
pinctrl-names = "default";
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
|
||||
bluetooth {
|
||||
/*
|
||||
* The BT is based on BCM4343A2. Murata 1YN variant seems to
|
||||
* require driving RTS on open.
|
||||
* Use compatible bcm43438 to accomplish this.
|
||||
*/
|
||||
compatible = "brcm,bcm43438-bt";
|
||||
max-speed = <115200>;
|
||||
shutdown-gpios = <&pinctrl RZG2L_GPIO(2, 3) GPIO_ACTIVE_HIGH>;
|
||||
vbat-supply = <®_pmic_buck4>;
|
||||
vddio-supply = <®_pmic_buck4>;
|
||||
};
|
||||
};
|
||||
|
||||
/* WiFi */
|
||||
&sdhi1 {
|
||||
/* Murata 1YN max rate is 50MHz */
|
||||
max-frequency = <50000000>;
|
||||
bus-width = <4>;
|
||||
cap-sdio-irq;
|
||||
mmc-pwrseq = <&sdhi1_pwrseq>;
|
||||
non-removable;
|
||||
no-1-8-v;
|
||||
no-sd;
|
||||
pinctrl-0 = <&sdhi1_pins>;
|
||||
pinctrl-names = "default";
|
||||
vmmc-supply = <®_pmic_buck4>;
|
||||
/*
|
||||
* Host controller IO voltage is provided from reg_pmic_ldo2,
|
||||
* WiFi module IO voltage from reg_pmic_buck4.
|
||||
* Neither is configurable at run-time so either can be set here.
|
||||
*/
|
||||
vqmmc-supply = <®_pmic_ldo2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy0 {
|
||||
vbus-supply = <&usb0_vbus_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdt0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -45,6 +45,12 @@ memory@48000000 {
|
|||
reg = <0x0 0x48000000 0x0 0x78000000>;
|
||||
};
|
||||
|
||||
pcie_refclk: pcie-ref-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
reg_1p0v: regulator-1p0v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-1.0V";
|
||||
|
|
@ -171,6 +177,11 @@ phy1: ethernet-phy@7 {
|
|||
};
|
||||
};
|
||||
|
||||
&pcie_port0 {
|
||||
clocks = <&pcie_refclk>;
|
||||
clock-names = "ref";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
eth0_pins: eth0 {
|
||||
txc {
|
||||
|
|
|
|||
59
include/dt-bindings/clock/renesas,r8a774a3-cpg-mssr.h
Normal file
59
include/dt-bindings/clock/renesas,r8a774a3-cpg-mssr.h
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (C) 2026 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_RENESAS_R8A774A3_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_RENESAS_R8A774A3_CPG_MSSR_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* r8a774a3 CPG Core Clocks */
|
||||
#define R8A774A3_CLK_Z 0
|
||||
#define R8A774A3_CLK_Z2 1
|
||||
#define R8A774A3_CLK_ZG 2
|
||||
#define R8A774A3_CLK_ZTR 3
|
||||
#define R8A774A3_CLK_ZTRD2 4
|
||||
#define R8A774A3_CLK_ZT 5
|
||||
#define R8A774A3_CLK_ZX 6
|
||||
#define R8A774A3_CLK_S0D1 7
|
||||
#define R8A774A3_CLK_S0D2 8
|
||||
#define R8A774A3_CLK_S0D3 9
|
||||
#define R8A774A3_CLK_S0D4 10
|
||||
#define R8A774A3_CLK_S0D6 11
|
||||
#define R8A774A3_CLK_S0D8 12
|
||||
#define R8A774A3_CLK_S0D12 13
|
||||
#define R8A774A3_CLK_S1D2 14
|
||||
#define R8A774A3_CLK_S1D4 15
|
||||
#define R8A774A3_CLK_S2D1 16
|
||||
#define R8A774A3_CLK_S2D2 17
|
||||
#define R8A774A3_CLK_S2D4 18
|
||||
#define R8A774A3_CLK_S3D1 19
|
||||
#define R8A774A3_CLK_S3D2 20
|
||||
#define R8A774A3_CLK_S3D4 21
|
||||
#define R8A774A3_CLK_LB 22
|
||||
#define R8A774A3_CLK_CL 23
|
||||
#define R8A774A3_CLK_ZB3 24
|
||||
#define R8A774A3_CLK_ZB3D2 25
|
||||
#define R8A774A3_CLK_ZB3D4 26
|
||||
#define R8A774A3_CLK_CR 27
|
||||
#define R8A774A3_CLK_CRD2 28
|
||||
#define R8A774A3_CLK_SD0H 29
|
||||
#define R8A774A3_CLK_SD0 30
|
||||
#define R8A774A3_CLK_SD1H 31
|
||||
#define R8A774A3_CLK_SD1 32
|
||||
#define R8A774A3_CLK_SD2H 33
|
||||
#define R8A774A3_CLK_SD2 34
|
||||
#define R8A774A3_CLK_SD3H 35
|
||||
#define R8A774A3_CLK_SD3 36
|
||||
#define R8A774A3_CLK_RPC 37
|
||||
#define R8A774A3_CLK_RPCD2 38
|
||||
#define R8A774A3_CLK_MSO 39
|
||||
#define R8A774A3_CLK_CANFD 40
|
||||
#define R8A774A3_CLK_HDMI 41
|
||||
#define R8A774A3_CLK_CSI0 42
|
||||
#define R8A774A3_CLK_CP 43
|
||||
#define R8A774A3_CLK_CPEX 44
|
||||
#define R8A774A3_CLK_R 45
|
||||
#define R8A774A3_CLK_OSC 46
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A774A3_CPG_MSSR_H__ */
|
||||
|
|
@ -10,5 +10,7 @@
|
|||
#define R8A78000_CPG_SGASYNCD4_PERW_BUS 0
|
||||
#define R8A78000_CPG_SGASYNCD8_PERW_BUS 1
|
||||
#define R8A78000_CPG_SGASYNCD16_PERW_BUS 2
|
||||
#define R8A78000_CPG_MSO_SCP_MAIN 3
|
||||
#define R8A78000_CPG_MSOCK_PERW_BUS 4
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A78000_CPG_H__ */
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@
|
|||
#define RPMHPD_GBX 22
|
||||
#define RPMHPD_NSP3 23
|
||||
#define RPMHPD_GFX1 24
|
||||
#define RPMHPD_NMXC 25
|
||||
|
||||
/* RPMh Power Domain performance levels */
|
||||
#define RPMH_REGULATOR_LEVEL_RETENTION 16
|
||||
|
|
|
|||
30
include/dt-bindings/power/renesas,r8a774a3-sysc.h
Normal file
30
include/dt-bindings/power/renesas,r8a774a3-sysc.h
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (C) 2026 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_RENESAS_R8A774A3_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_RENESAS_R8A774A3_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits
|
||||
* representing the power areas in the various Interrupt Registers
|
||||
* (e.g. SYSCISR, Interrupt Status Register)
|
||||
*/
|
||||
|
||||
#define R8A774A3_PD_CA57_CPU0 0
|
||||
#define R8A774A3_PD_CA57_CPU1 1
|
||||
#define R8A774A3_PD_CA53_CPU0 5
|
||||
#define R8A774A3_PD_CA53_CPU1 6
|
||||
#define R8A774A3_PD_CA53_CPU2 7
|
||||
#define R8A774A3_PD_CA53_CPU3 8
|
||||
#define R8A774A3_PD_CA57_SCU 12
|
||||
#define R8A774A3_PD_A3VC 14
|
||||
#define R8A774A3_PD_3DG_A 17
|
||||
#define R8A774A3_PD_3DG_B 18
|
||||
#define R8A774A3_PD_CA53_SCU 21
|
||||
#define R8A774A3_PD_A2VC1 26
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A774A3_PD_ALWAYS_ON 32
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_RENESAS_R8A774A3_SYSC_H__ */
|
||||
Loading…
Reference in New Issue
Block a user