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ARM: dts: aspeed: Add LPC reset controller node

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On both the ast2400 and ast2500 SoCs, the LPC reset controller is
required to bring the UARTs out of reset without waiting for the LPC
reset to be deasserted.

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
This commit is contained in:
Joel Stanley 2018-02-19 18:05:40 +10:30
parent f4c3735456
commit fd2de0a731
2 changed files with 20 additions and 0 deletions
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10
arch/arm/boot/dts/aspeed-g4.dtsi
View File

@ -162,6 +162,7 @@ uart1: serial@1e783000 {
reg-shift = <2>;
interrupts = <9>;
clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
resets = <&lpc_reset 4>;
no-loopback-test;
status = "disabled";
};
@ -249,6 +250,12 @@ lhc: lhc@20 {
reg = <0x20 0x24 0x48 0x8>;
};
lpc_reset: reset-controller@18 {
compatible = "aspeed,ast2400-lpc-reset";
reg = <0x18 0x4>;
#reset-cells = <1>;
};
ibt: ibt@c0 {
compatible = "aspeed,ast2400-ibt-bmc";
reg = <0xc0 0x18>;
@ -264,6 +271,7 @@ uart2: serial@1e78d000 {
reg-shift = <2>;
interrupts = <32>;
clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
resets = <&lpc_reset 5>;
no-loopback-test;
status = "disabled";
};
@ -274,6 +282,7 @@ uart3: serial@1e78e000 {
reg-shift = <2>;
interrupts = <33>;
clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
resets = <&lpc_reset 6>;
no-loopback-test;
status = "disabled";
};
@ -284,6 +293,7 @@ uart4: serial@1e78f000 {
reg-shift = <2>;
interrupts = <34>;
clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
resets = <&lpc_reset 7>;
no-loopback-test;
status = "disabled";
};

10
arch/arm/boot/dts/aspeed-g5.dtsi
View File

@ -205,6 +205,7 @@ uart1: serial@1e783000 {
reg-shift = <2>;
interrupts = <9>;
clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
resets = <&lpc_reset 4>;
no-loopback-test;
status = "disabled";
};
@ -299,6 +300,12 @@ lhc: lhc@20 {
reg = <0x20 0x24 0x48 0x8>;
};
lpc_reset: reset-controller@18 {
compatible = "aspeed,ast2500-lpc-reset";
reg = <0x18 0x4>;
#reset-cells = <1>;
};
ibt: ibt@c0 {
compatible = "aspeed,ast2500-ibt-bmc";
reg = <0xc0 0x18>;
@ -314,6 +321,7 @@ uart2: serial@1e78d000 {
reg-shift = <2>;
interrupts = <32>;
clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
resets = <&lpc_reset 5>;
no-loopback-test;
status = "disabled";
};
@ -324,6 +332,7 @@ uart3: serial@1e78e000 {
reg-shift = <2>;
interrupts = <33>;
clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
resets = <&lpc_reset 6>;
no-loopback-test;
status = "disabled";
};
@ -334,6 +343,7 @@ uart4: serial@1e78f000 {
reg-shift = <2>;
interrupts = <34>;
clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
resets = <&lpc_reset 7>;
no-loopback-test;
status = "disabled";
};