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arm64: dts: ls1028a: add l1 and l2 cache info

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When we ran the stress-ng cache related stressors, we got the log as
below:
ubuntu@ubuntu:~$ stress-ng --l1cache 4
stress-ng: info:  [656] defaulting to a 86400 second (1 day, 0.00 secs) run per stressor
stress-ng: info:  [656] dispatching hogs: 4 l1cache
stress-ng: info:  [657] stress-ng-l1cache: skipping stressor, cannot determine cache level 1 information from kernel

This is because the l1 and l2 cache info is missing in the devicetree,
ls1028a has dual cortex-a72 cores and has 48KB icache, 32KB dcache and
1MB l2 ucache:
  - icache is 3-way set associative
  - dcache is 2-way set associative
  - l2cache is 16-way set associative
  - line size are 64bytes

Signed-off-by: Hui Wang <hui.wang@canonical.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Hui Wang 2023-07-31 16:46:14 +08:00 committed by Shawn Guo
parent aca2687021
commit fcf7ff67a2
1 changed files with 15 additions and 0 deletions
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15
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
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@ -28,6 +28,12 @@ cpu0: cpu@0 {
reg = <0x0>;
enable-method = "psci";
clocks = <&clockgen QORIQ_CLK_CMUX 0>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PW20>;
#cooling-cells = <2>;
@ -39,6 +45,12 @@ cpu1: cpu@1 {
reg = <0x1>;
enable-method = "psci";
clocks = <&clockgen QORIQ_CLK_CMUX 0>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PW20>;
#cooling-cells = <2>;
@ -48,6 +60,9 @@ l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
};
};