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arm64: zynqmp: Switch to ethernet-phy-id in kv260

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Use ethernet-phy-id compatible string to properly describe phy reset on
kv260 boards. Previous description wasn't correct because reset was done
for mdio bus to operate and it was in this case used for different purpose
which was eth phy reset. With ethernet-phy-id phy reset happens only for
the phy via phy framework.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/4b139e942c2a808eecbb30226b6ea5303348390a.1683034376.git.michal.simek@amd.com
This commit is contained in:
Michal Simek 2023-05-02 15:35:45 +02:00
parent 60a9905424
commit fc57b6c929
2 changed files with 8 additions and 4 deletions
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6
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
View File

@ -145,16 +145,18 @@ &gem3 { /* required by spec */
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
reset-delay-us = <2>;
phy0: ethernet-phy@1 {
#phy-cells = <1>;
reg = <1>;
compatible = "ethernet-phy-id2000.a231";
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
reset-assert-us = <100>;
reset-deassert-us = <280>;
reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
};
};
};

6
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
View File

@ -128,16 +128,18 @@ &gem3 { /* required by spec */
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
reset-delay-us = <2>;
phy0: ethernet-phy@1 {
#phy-cells = <1>;
reg = <1>;
compatible = "ethernet-phy-id2000.a231";
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
reset-assert-us = <100>;
reset-deassert-us = <280>;
reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
};
};
};