wifi: rtw89: add addr cam H2C command v1

The coming RTL8922D uses different format of address CAM command, so add
the new format accordingly.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20251114060128.35363-13-pkshih@realtek.com
This commit is contained in:
Ping-Ke Shih 2025-11-14 14:01:26 +08:00
parent 239dd70d77
commit fc2e8c873f
9 changed files with 46 additions and 11 deletions

View File

@ -819,12 +819,15 @@ void rtw89_cam_fill_addr_cam_info(struct rtw89_dev *rtwdev,
struct rtw89_addr_cam_entry *addr_cam =
rtw89_get_addr_cam_of(rtwvif_link, rtwsta_link);
struct ieee80211_sta *sta = rtwsta_link_to_sta_safe(rtwsta_link);
const struct rtw89_chip_info *chip = rtwdev->chip;
struct ieee80211_link_sta *link_sta;
const u8 *sma = scan_mac_addr ? scan_mac_addr : rtwvif_link->mac_addr;
u8 sma_hash, tma_hash, addr_msk_start;
u8 ver = chip->addrcam_ver;
u8 sma_start = 0;
u8 tma_start = 0;
const u8 *tma;
u8 mac_id;
rcu_read_lock();
@ -845,9 +848,17 @@ void rtw89_cam_fill_addr_cam_info(struct rtw89_dev *rtwdev,
sma_hash = rtw89_cam_addr_hash(sma_start, sma);
tma_hash = rtw89_cam_addr_hash(tma_start, tma);
h2c->w1 = le32_encode_bits(addr_cam->addr_cam_idx, ADDR_CAM_W1_IDX) |
le32_encode_bits(addr_cam->offset, ADDR_CAM_W1_OFFSET) |
le32_encode_bits(addr_cam->len, ADDR_CAM_W1_LEN);
mac_id = rtwsta_link ? rtwsta_link->mac_id : rtwvif_link->mac_id;
if (ver == 0)
h2c->w1 = le32_encode_bits(addr_cam->addr_cam_idx, ADDR_CAM_W1_IDX) |
le32_encode_bits(addr_cam->offset, ADDR_CAM_W1_OFFSET) |
le32_encode_bits(addr_cam->len, ADDR_CAM_W1_LEN);
else
h2c->w1 = le32_encode_bits(addr_cam->addr_cam_idx, ADDR_CAM_W1_V1_IDX) |
le32_encode_bits(addr_cam->offset, ADDR_CAM_W1_V1_OFFSET) |
le32_encode_bits(addr_cam->len, ADDR_CAM_W1_V1_LEN);
h2c->w2 = le32_encode_bits(addr_cam->valid, ADDR_CAM_W2_VALID) |
le32_encode_bits(rtwvif_link->net_type, ADDR_CAM_W2_NET_TYPE) |
le32_encode_bits(rtwvif_link->bcn_hit_cond, ADDR_CAM_W2_BCN_HIT_COND) |
@ -870,14 +881,20 @@ void rtw89_cam_fill_addr_cam_info(struct rtw89_dev *rtwdev,
le32_encode_bits(tma[3], ADDR_CAM_W6_TMA3) |
le32_encode_bits(tma[4], ADDR_CAM_W6_TMA4) |
le32_encode_bits(tma[5], ADDR_CAM_W6_TMA5);
h2c->w8 = le32_encode_bits(rtwvif_link->port, ADDR_CAM_W8_PORT_INT) |
le32_encode_bits(rtwvif_link->port, ADDR_CAM_W8_TSF_SYNC) |
le32_encode_bits(rtwvif_link->trigger, ADDR_CAM_W8_TF_TRS) |
le32_encode_bits(rtwvif_link->lsig_txop, ADDR_CAM_W8_LSIG_TXOP) |
le32_encode_bits(rtwvif_link->tgt_ind, ADDR_CAM_W8_TGT_IND) |
le32_encode_bits(rtwvif_link->frm_tgt_ind, ADDR_CAM_W8_FRM_TGT_IND) |
le32_encode_bits(rtwsta_link ? rtwsta_link->mac_id :
rtwvif_link->mac_id, ADDR_CAM_W8_MACID);
if (ver == 0)
h2c->w8 = le32_encode_bits(rtwvif_link->port, ADDR_CAM_W8_PORT_INT) |
le32_encode_bits(rtwvif_link->port, ADDR_CAM_W8_TSF_SYNC) |
le32_encode_bits(rtwvif_link->trigger, ADDR_CAM_W8_TF_TRS) |
le32_encode_bits(rtwvif_link->lsig_txop, ADDR_CAM_W8_LSIG_TXOP) |
le32_encode_bits(rtwvif_link->tgt_ind, ADDR_CAM_W8_TGT_IND) |
le32_encode_bits(rtwvif_link->frm_tgt_ind, ADDR_CAM_W8_FRM_TGT_IND) |
le32_encode_bits(mac_id, ADDR_CAM_W8_MACID);
else
h2c->w8 = le32_encode_bits(rtwvif_link->port, ADDR_CAM_W8_V1_PORT_INT) |
le32_encode_bits(rtwvif_link->port, ADDR_CAM_W8_V1_TSF_SYNC) |
le32_encode_bits(rtwvif_link->trigger, ADDR_CAM_W8_V1_TF_TRS) |
le32_encode_bits(rtwvif_link->lsig_txop, ADDR_CAM_W8_V1_LSIG_TXOP) |
le32_encode_bits(mac_id, ADDR_CAM_W8_V1_MACID);
if (rtwvif_link->net_type == RTW89_NET_TYPE_INFRA)
h2c->w9 = le32_encode_bits(vif->cfg.aid & 0xfff, ADDR_CAM_W9_AID12);

View File

@ -33,6 +33,9 @@ struct rtw89_h2c_addr_cam {
#define ADDR_CAM_W1_IDX GENMASK(7, 0)
#define ADDR_CAM_W1_OFFSET GENMASK(15, 8)
#define ADDR_CAM_W1_LEN GENMASK(23, 16)
#define ADDR_CAM_W1_V1_IDX GENMASK(9, 0)
#define ADDR_CAM_W1_V1_OFFSET GENMASK(23, 16)
#define ADDR_CAM_W1_V1_LEN GENMASK(31, 24)
#define ADDR_CAM_W2_VALID BIT(0)
#define ADDR_CAM_W2_NET_TYPE GENMASK(2, 1)
#define ADDR_CAM_W2_BCN_HIT_COND GENMASK(4, 3)
@ -62,6 +65,14 @@ struct rtw89_h2c_addr_cam {
#define ADDR_CAM_W8_LSIG_TXOP BIT(15)
#define ADDR_CAM_W8_TGT_IND GENMASK(26, 24)
#define ADDR_CAM_W8_FRM_TGT_IND GENMASK(29, 27)
#define ADDR_CAM_W8_V1_MACID GENMASK(9, 0)
#define ADDR_CAM_W8_V1_PORT_INT GENMASK(18, 16)
#define ADDR_CAM_W8_V1_TSF_SYNC GENMASK(21, 19)
#define ADDR_CAM_W8_V1_TF_TRS BIT(22)
#define ADDR_CAM_W8_V1_LSIG_TXOP BIT(23)
#define ADDR_CAM_W8_V1_TB_RANGING BIT(24)
#define ADDR_CAM_W8_V1_TB_SENSING BIT(25)
#define ADDR_CAM_W8_V1_SENS_EN BIT(26)
#define ADDR_CAM_W9_AID12 GENMASK(11, 0)
#define ADDR_CAM_W9_AID12_0 GENMASK(7, 0)
#define ADDR_CAM_W9_AID12_1 GENMASK(11, 8)

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@ -4458,6 +4458,7 @@ struct rtw89_chip_info {
u8 bacam_num;
u8 bacam_dynamic_num;
enum rtw89_bacam_ver bacam_ver;
u8 addrcam_ver;
u8 ppdu_max_usr;
u8 sec_ctrl_efuse_size;

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@ -2648,6 +2648,7 @@ const struct rtw89_chip_info rtw8851b_chip_info = {
.bacam_num = 2,
.bacam_dynamic_num = 4,
.bacam_ver = RTW89_BACAM_V0,
.addrcam_ver = 0,
.ppdu_max_usr = 4,
.sec_ctrl_efuse_size = 4,
.physical_efuse_size = 1216,

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@ -2334,6 +2334,7 @@ const struct rtw89_chip_info rtw8852a_chip_info = {
.bacam_num = 2,
.bacam_dynamic_num = 4,
.bacam_ver = RTW89_BACAM_V0,
.addrcam_ver = 0,
.ppdu_max_usr = 4,
.sec_ctrl_efuse_size = 4,
.physical_efuse_size = 1216,

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@ -959,6 +959,7 @@ const struct rtw89_chip_info rtw8852b_chip_info = {
.bacam_num = 2,
.bacam_dynamic_num = 4,
.bacam_ver = RTW89_BACAM_V0,
.addrcam_ver = 0,
.ppdu_max_usr = 4,
.sec_ctrl_efuse_size = 4,
.physical_efuse_size = 1216,

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@ -818,6 +818,7 @@ const struct rtw89_chip_info rtw8852bt_chip_info = {
.bacam_num = 2,
.bacam_dynamic_num = 4,
.bacam_ver = RTW89_BACAM_V0,
.addrcam_ver = 0,
.ppdu_max_usr = 4,
.sec_ctrl_efuse_size = 4,
.physical_efuse_size = 1216,

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@ -3178,6 +3178,7 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
.bacam_num = 8,
.bacam_dynamic_num = 8,
.bacam_ver = RTW89_BACAM_V0_EXT,
.addrcam_ver = 0,
.ppdu_max_usr = 8,
.sec_ctrl_efuse_size = 4,
.physical_efuse_size = 1216,

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@ -2931,6 +2931,7 @@ const struct rtw89_chip_info rtw8922a_chip_info = {
.bacam_num = 24,
.bacam_dynamic_num = 8,
.bacam_ver = RTW89_BACAM_V1,
.addrcam_ver = 0,
.ppdu_max_usr = 16,
.sec_ctrl_efuse_size = 4,
.physical_efuse_size = 0x1300,