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Merge patch series "can: rcar_canfd: R-Car CANFD Improvements"

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Biju <biju.das.au@gmail.com> says:

From: Biju Das <biju.das.jz@bp.renesas.com>

The calculation formula for nominal bit rate of classical CAN is same as
that of nominal bit rate of CANFD on the RZ/G3E SoC and R-Car Gen4
compared to other SoCs. Update the nominal bit rate constants.

Apart from this, for replacing function-like macros, introduced
rcar_canfd_compute_{nominal,data}_bit_rate_cfg().

v2->v3:
 * Replaced "shared_bittiming"->"shared_can_regs" as it is same for RZ/G3E
   and R-Car Gen4.
 * Updated commit header and description for patch#1.
 * Added Rb tag from Geert for patch #2,#3 and #4.
 * Dropped _MASK suffix from RCANFD_CFG_* macros.
 * Dropped _MASK suffix from RCANFD_NCFG_NBRP_MASK macro.
 * Dropped _MASK suffix from the macro RCANFD_DCFG_DBRP_MASK.
 * Followed the order as used in struct can_bittiming{_const} for easy
   maintenance.
v1->v2:
 * Dropped patch#2 as it is accepted.
 * Moved patch#4 to patch#2.
 * Updated commit header and description for patch#2.
 * Kept RCANFD_CFG* macro definitions to give a meaning to the magic
   number using GENMASK macro and used FIELD_PREP to extract value.
 * Split patch#3 for computing nominal  and data bit rate config separate.
 * Updated rcar_canfd_compute_nominal_bit_rate_cfg() to handle
   nominal bit rate configuration for both classical CAN and CANFD.
 * Replaced RCANFD_NCFG_NBRP->RCANFD_NCFG_NBRP_MASK and used FIELD_PREP to
   extract value.
 * Replaced RCANFD_DCFG_DBRP->RCANFD_DCFG_DBRP_MASK and used FIELD_PREP to
   extract value.

Link: https://patch.msgid.link/20250908120940.147196-1-biju.das.jz@bp.renesas.com
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
This commit is contained in:
Marc Kleine-Budde 2025-09-13 19:07:28 +02:00
commit fbfa8f4f3d
1 changed files with 47 additions and 37 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

84
drivers/net/can/rcar/rcar_canfd.c
View File

@ -103,22 +103,13 @@
/* Channel register bits */
/* RSCFDnCmCFG - Classical CAN only */
#define RCANFD_CFG_SJW(x) (((x) & 0x3) << 24)
#define RCANFD_CFG_TSEG2(x) (((x) & 0x7) << 20)
#define RCANFD_CFG_TSEG1(x) (((x) & 0xf) << 16)
#define RCANFD_CFG_BRP(x) (((x) & 0x3ff) << 0)
#define RCANFD_CFG_SJW GENMASK(25, 24)
#define RCANFD_CFG_TSEG2 GENMASK(22, 20)
#define RCANFD_CFG_TSEG1 GENMASK(19, 16)
#define RCANFD_CFG_BRP GENMASK(9, 0)
/* RSCFDnCFDCmNCFG - CAN FD only */
#define RCANFD_NCFG_NTSEG2(gpriv, x) \
(((x) & ((gpriv)->info->nom_bittiming->tseg2_max - 1)) << (gpriv)->info->sh->ntseg2)
#define RCANFD_NCFG_NTSEG1(gpriv, x) \
(((x) & ((gpriv)->info->nom_bittiming->tseg1_max - 1)) << (gpriv)->info->sh->ntseg1)
#define RCANFD_NCFG_NSJW(gpriv, x) \
(((x) & ((gpriv)->info->nom_bittiming->sjw_max - 1)) << (gpriv)->info->sh->nsjw)
#define RCANFD_NCFG_NBRP(x) (((x) & 0x3ff) << 0)
#define RCANFD_NCFG_NBRP GENMASK(9, 0)
/* RSCFDnCFDCmCTR / RSCFDnCmCTR */
#define RCANFD_CCTR_CTME BIT(24)
@ -178,15 +169,7 @@
#define RCANFD_CERFL_ERR(x) ((x) & (0x7fff)) /* above bits 14:0 */
/* RSCFDnCFDCmDCFG */
#define RCANFD_DCFG_DSJW(gpriv, x) (((x) & ((gpriv)->info->data_bittiming->sjw_max - 1)) << 24)
#define RCANFD_DCFG_DTSEG2(gpriv, x) \
(((x) & ((gpriv)->info->data_bittiming->tseg2_max - 1)) << (gpriv)->info->sh->dtseg2)
#define RCANFD_DCFG_DTSEG1(gpriv, x) \
(((x) & ((gpriv)->info->data_bittiming->tseg1_max - 1)) << (gpriv)->info->sh->dtseg1)
#define RCANFD_DCFG_DBRP(x) (((x) & 0xff) << 0)
#define RCANFD_DCFG_DBRP GENMASK(7, 0)
/* RSCFDnCFDCmFDCFG */
#define RCANFD_GEN4_FDCFG_CLOE BIT(30)
@ -1388,6 +1371,41 @@ static irqreturn_t rcar_canfd_channel_interrupt(int irq, void *dev_id)
return IRQ_HANDLED;
}
static inline u32 rcar_canfd_compute_nominal_bit_rate_cfg(struct rcar_canfd_channel *priv,
u16 tseg1, u16 tseg2, u16 sjw, u16 brp)
{
struct rcar_canfd_global *gpriv = priv->gpriv;
const struct rcar_canfd_hw_info *info = gpriv->info;
u32 ntseg1, ntseg2, nsjw, nbrp;
if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) || gpriv->info->shared_can_regs) {
ntseg1 = (tseg1 & (info->nom_bittiming->tseg1_max - 1)) << info->sh->ntseg1;
ntseg2 = (tseg2 & (info->nom_bittiming->tseg2_max - 1)) << info->sh->ntseg2;
nsjw = (sjw & (info->nom_bittiming->sjw_max - 1)) << info->sh->nsjw;
nbrp = FIELD_PREP(RCANFD_NCFG_NBRP, brp);
} else {
ntseg1 = FIELD_PREP(RCANFD_CFG_TSEG1, tseg1);
ntseg2 = FIELD_PREP(RCANFD_CFG_TSEG2, tseg2);
nsjw = FIELD_PREP(RCANFD_CFG_SJW, sjw);
nbrp = FIELD_PREP(RCANFD_CFG_BRP, brp);
}
return (ntseg1 | ntseg2 | nsjw | nbrp);
}
static inline u32 rcar_canfd_compute_data_bit_rate_cfg(const struct rcar_canfd_hw_info *info,
u16 tseg1, u16 tseg2, u16 sjw, u16 brp)
{
u32 dtseg1, dtseg2, dsjw, dbrp;
dtseg1 = (tseg1 & (info->data_bittiming->tseg1_max - 1)) << info->sh->dtseg1;
dtseg2 = (tseg2 & (info->data_bittiming->tseg2_max - 1)) << info->sh->dtseg2;
dsjw = (sjw & (info->data_bittiming->sjw_max - 1)) << 24;
dbrp = FIELD_PREP(RCANFD_DCFG_DBRP, brp);
return (dtseg1 | dtseg2 | dsjw | dbrp);
}
static void rcar_canfd_set_bittiming(struct net_device *ndev)
{
u32 mask = RCANFD_FDCFG_TDCO | RCANFD_FDCFG_TDCE | RCANFD_FDCFG_TDCOC;
@ -1406,15 +1424,7 @@ static void rcar_canfd_set_bittiming(struct net_device *ndev)
sjw = bt->sjw - 1;
tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
tseg2 = bt->phase_seg2 - 1;
if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) || gpriv->info->shared_can_regs) {
cfg = (RCANFD_NCFG_NTSEG1(gpriv, tseg1) | RCANFD_NCFG_NBRP(brp) |
RCANFD_NCFG_NSJW(gpriv, sjw) | RCANFD_NCFG_NTSEG2(gpriv, tseg2));
} else {
cfg = (RCANFD_CFG_TSEG1(tseg1) | RCANFD_CFG_BRP(brp) |
RCANFD_CFG_SJW(sjw) | RCANFD_CFG_TSEG2(tseg2));
}
cfg = rcar_canfd_compute_nominal_bit_rate_cfg(priv, tseg1, tseg2, sjw, brp);
rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD))
@ -1425,10 +1435,7 @@ static void rcar_canfd_set_bittiming(struct net_device *ndev)
sjw = dbt->sjw - 1;
tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
tseg2 = dbt->phase_seg2 - 1;
cfg = (RCANFD_DCFG_DTSEG1(gpriv, tseg1) | RCANFD_DCFG_DBRP(brp) |
RCANFD_DCFG_DSJW(gpriv, sjw) | RCANFD_DCFG_DTSEG2(gpriv, tseg2));
cfg = rcar_canfd_compute_data_bit_rate_cfg(gpriv->info, tseg1, tseg2, sjw, brp);
writel(cfg, &gpriv->fcbase[ch].dcfg);
/* Transceiver Delay Compensation */
@ -1912,7 +1919,10 @@ static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch,
priv->can.fd.do_get_auto_tdcv = rcar_canfd_get_auto_tdcv;
} else {
/* Controller starts in Classical CAN only mode */
priv->can.bittiming_const = &rcar_canfd_bittiming_const;
if (gpriv->info->shared_can_regs)
priv->can.bittiming_const = gpriv->info->nom_bittiming;
else
priv->can.bittiming_const = &rcar_canfd_bittiming_const;
priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
}