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dt-bindings: media: Convert MediaTek mt8173-mdp bindings to DT schema
Convert the existing text-based DT bindings for MediaTek MT8173 Media Data Path to a DT schema. Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://patch.msgid.link/20251001183115.83111-1-ariel.dalessandro@collabora.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
This commit is contained in:
Ariel D'Alessandro
Rob Herring (Arm)
parent
fc75109288
commit
fbf97d6c1d
169
Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml
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169
Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml
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@ -0,0 +1,169 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/mediatek,mt8173-mdp.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek MT8173 Media Data Path
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maintainers:
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- Ariel D'Alessandro <ariel.dalessandro@collabora.com>
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description:
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Media Data Path is used for scaling and color space conversion.
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properties:
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compatible:
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oneOf:
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- enum:
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- mediatek,mt8173-mdp-rdma
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- mediatek,mt8173-mdp-rsz
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- mediatek,mt8173-mdp-wdma
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- mediatek,mt8173-mdp-wrot
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- items:
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- const: mediatek,mt8173-mdp-rdma
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- const: mediatek,mt8173-mdp
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reg:
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maxItems: 1
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clocks:
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minItems: 1
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maxItems: 2
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power-domains:
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maxItems: 1
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iommus:
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maxItems: 1
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mediatek,vpu:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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phandle to Mediatek Video Processor Unit for HW Codec encode/decode and
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image processing.
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required:
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- compatible
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- reg
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- clocks
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- power-domains
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: mediatek,mt8173-mdp-rdma
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then:
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properties:
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clocks:
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items:
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- description: Main clock
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- description: Mutex clock
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else:
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properties:
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clocks:
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items:
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- description: Main clock
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- if:
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properties:
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compatible:
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contains:
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enum:
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- mediatek,mt8173-mdp-rdma
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- mediatek,mt8173-mdp-wdma
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- mediatek,mt8173-mdp-wrot
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then:
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required:
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- iommus
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- if:
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properties:
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compatible:
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contains:
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const: mediatek,mt8173-mdp
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then:
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required:
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- mediatek,vpu
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt8173-clk.h>
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#include <dt-bindings/memory/mt8173-larb-port.h>
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#include <dt-bindings/power/mt8173-power.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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mdp_rdma0: rdma@14001000 {
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compatible = "mediatek,mt8173-mdp-rdma",
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"mediatek,mt8173-mdp";
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reg = <0 0x14001000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_RDMA0>,
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<&mmsys CLK_MM_MUTEX_32K>;
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power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
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iommus = <&iommu M4U_PORT_MDP_RDMA0>;
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mediatek,vpu = <&vpu>;
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};
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mdp_rdma1: rdma@14002000 {
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compatible = "mediatek,mt8173-mdp-rdma";
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reg = <0 0x14002000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_RDMA1>,
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<&mmsys CLK_MM_MUTEX_32K>;
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power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
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iommus = <&iommu M4U_PORT_MDP_RDMA1>;
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};
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mdp_rsz0: rsz@14003000 {
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compatible = "mediatek,mt8173-mdp-rsz";
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reg = <0 0x14003000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_RSZ0>;
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power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
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};
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mdp_rsz1: rsz@14004000 {
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compatible = "mediatek,mt8173-mdp-rsz";
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reg = <0 0x14004000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_RSZ1>;
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power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
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};
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mdp_rsz2: rsz@14005000 {
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compatible = "mediatek,mt8173-mdp-rsz";
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reg = <0 0x14005000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_RSZ2>;
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power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
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};
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mdp_wdma0: wdma@14006000 {
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compatible = "mediatek,mt8173-mdp-wdma";
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reg = <0 0x14006000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_WDMA>;
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power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
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iommus = <&iommu M4U_PORT_MDP_WDMA>;
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};
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mdp_wrot0: wrot@14007000 {
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compatible = "mediatek,mt8173-mdp-wrot";
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reg = <0 0x14007000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_WROT0>;
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power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
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iommus = <&iommu M4U_PORT_MDP_WROT0>;
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};
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mdp_wrot1: wrot@14008000 {
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compatible = "mediatek,mt8173-mdp-wrot";
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reg = <0 0x14008000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_WROT1>;
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power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
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iommus = <&iommu M4U_PORT_MDP_WROT1>;
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};
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};
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...
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@ -1,96 +0,0 @@
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* Mediatek Media Data Path
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Media Data Path is used for scaling and color space conversion.
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Required properties (controller node):
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- compatible: "mediatek,mt8173-mdp"
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- mediatek,vpu: the node of video processor unit, see
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Documentation/devicetree/bindings/media/mediatek,mt8173-vpu.yaml for
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details.
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Required properties (all function blocks, child node):
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- compatible: Should be one of
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"mediatek,mt8173-mdp-rdma" - read DMA
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"mediatek,mt8173-mdp-rsz" - resizer
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"mediatek,mt8173-mdp-wdma" - write DMA
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"mediatek,mt8173-mdp-wrot" - write DMA with rotation
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- reg: Physical base address and length of the function block register space
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- clocks: device clocks, see
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Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
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- power-domains: a phandle to the power domain, see
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Documentation/devicetree/bindings/power/power_domain.txt for details.
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Required properties (DMA function blocks, child node):
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- compatible: Should be one of
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"mediatek,mt8173-mdp-rdma"
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"mediatek,mt8173-mdp-wdma"
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"mediatek,mt8173-mdp-wrot"
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- iommus: should point to the respective IOMMU block with master port as
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argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
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for details.
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Example:
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mdp_rdma0: rdma@14001000 {
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compatible = "mediatek,mt8173-mdp-rdma";
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"mediatek,mt8173-mdp";
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reg = <0 0x14001000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_RDMA0>,
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<&mmsys CLK_MM_MUTEX_32K>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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iommus = <&iommu M4U_PORT_MDP_RDMA0>;
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mediatek,vpu = <&vpu>;
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};
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mdp_rdma1: rdma@14002000 {
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compatible = "mediatek,mt8173-mdp-rdma";
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reg = <0 0x14002000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_RDMA1>,
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<&mmsys CLK_MM_MUTEX_32K>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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iommus = <&iommu M4U_PORT_MDP_RDMA1>;
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};
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mdp_rsz0: rsz@14003000 {
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compatible = "mediatek,mt8173-mdp-rsz";
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reg = <0 0x14003000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_RSZ0>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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};
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mdp_rsz1: rsz@14004000 {
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compatible = "mediatek,mt8173-mdp-rsz";
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reg = <0 0x14004000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_RSZ1>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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};
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mdp_rsz2: rsz@14005000 {
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compatible = "mediatek,mt8173-mdp-rsz";
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reg = <0 0x14005000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_RSZ2>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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};
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mdp_wdma0: wdma@14006000 {
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compatible = "mediatek,mt8173-mdp-wdma";
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reg = <0 0x14006000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_WDMA>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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iommus = <&iommu M4U_PORT_MDP_WDMA>;
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};
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mdp_wrot0: wrot@14007000 {
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compatible = "mediatek,mt8173-mdp-wrot";
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reg = <0 0x14007000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_WROT0>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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iommus = <&iommu M4U_PORT_MDP_WROT0>;
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};
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mdp_wrot1: wrot@14008000 {
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compatible = "mediatek,mt8173-mdp-wrot";
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reg = <0 0x14008000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_WROT1>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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iommus = <&iommu M4U_PORT_MDP_WROT1>;
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};
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