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dt-bindings: fpga: altr,fpga-passive-serial: Convert to yaml

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Convert the Altera Passive Serial SPI FPGA Manager binding
from text file to yaml format to allow devicetree validation.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20241003104230.1628813-1-festevam@gmail.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
This commit is contained in:
Fabio Estevam 2024-10-03 07:42:30 -03:00 committed by Rob Herring (Arm)
parent a6fa1f9e32
commit fbe4ba6c5c
2 changed files with 74 additions and 29 deletions
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29
Documentation/devicetree/bindings/fpga/altera-passive-serial.txt
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Altera Passive Serial SPI FPGA Manager
Altera FPGAs support a method of loading the bitstream over what is
referred to as "passive serial".
The passive serial link is not technically SPI, and might require extra
circuits in order to play nicely with other SPI slaves on the same bus.
See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf
Required properties:
- compatible: Must be one of the following:
"altr,fpga-passive-serial",
"altr,fpga-arria10-passive-serial"
- reg: SPI chip select of the FPGA
- nconfig-gpios: config pin (referred to as nCONFIG in the manual)
- nstat-gpios: status pin (referred to as nSTATUS in the manual)
Optional properties:
- confd-gpios: confd pin (referred to as CONF_DONE in the manual)
Example:
fpga: fpga@0 {
compatible = "altr,fpga-passive-serial";
spi-max-frequency = <20000000>;
reg = <0>;
nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
confd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
};

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Documentation/devicetree/bindings/fpga/altr,fpga-passive-serial.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/fpga/altr,fpga-passive-serial.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Altera Passive Serial SPI FPGA Manager
maintainers:
- Fabio Estevam <festevam@denx.de>
description: |
Altera FPGAs support a method of loading the bitstream over what is
referred to as "passive serial".
The passive serial link is not technically SPI, and might require extra
circuits in order to play nicely with other SPI slaves on the same bus.
See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf
allOf:
- $ref: /schemas/spi/spi-peripheral-props.yaml#
properties:
compatible:
enum:
- altr,fpga-passive-serial
- altr,fpga-arria10-passive-serial
spi-max-frequency:
maximum: 20000000
reg:
maxItems: 1
nconfig-gpios:
description:
Config pin (referred to as nCONFIG in the manual).
maxItems: 1
nstat-gpios:
description:
Status pin (referred to as nSTATUS in the manual).
maxItems: 1
confd-gpios:
description:
confd pin (referred to as CONF_DONE in the manual)
maxItems: 1
required:
- compatible
- reg
- nconfig-gpios
- nstat-gpios
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
fpga@0 {
compatible = "altr,fpga-passive-serial";
reg = <0>;
nconfig-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
nstat-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
confd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
};
};
...