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clk: rockchip: Temporarily fix for rk3588 pll

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Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I15819f3611556e140ec80126b990408edf260c18
This commit is contained in:
Tao Huang 2021-11-11 17:18:31 +08:00
parent e0e8de4a77
commit fb7d7606a1
1 changed files with 3 additions and 0 deletions
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3
drivers/clk/rockchip/clk-pll.c
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@ -1268,6 +1268,9 @@ static int rockchip_rk3588_pll_wait_lock(struct rockchip_clk_pll *pll)
u32 pllcon;
int ret;
for (ret = 0; ret < 1000; ret++)
asm("nop");
return 0;
/*
* Lock time typical 250, max 500 input clock cycles @24MHz
* So define a very safe maximum of 1000us, meaning 24000 cycles.