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drm: renesas: rz-du: mipi_dsi: Set DSI divider

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Before the MIPI DSI clock source can be configured, the target divide
ratio needs to be set.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
Fixes: 5a4326f2e3 ("clk: renesas: rzg2l: Remove DSI clock rate restrictions")
Link: https://patch.msgid.link/20260227015216.2721504-1-chris.brandt@renesas.com
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
This commit is contained in:
Chris Brandt 2026-02-26 20:52:16 -05:00 committed by Biju Das
parent 89ff45359a
commit fb797a7010
1 changed files with 15 additions and 1 deletions
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16
drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
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@ -1122,6 +1122,7 @@ static int rzg2l_mipi_dsi_host_attach(struct mipi_dsi_host *host,
struct mipi_dsi_device *device) struct mipi_dsi_device *device)
{ {
struct rzg2l_mipi_dsi *dsi = host_to_rzg2l_mipi_dsi(host); struct rzg2l_mipi_dsi *dsi = host_to_rzg2l_mipi_dsi(host);
int bpp;
int ret; int ret;
if (device->lanes > dsi->num_data_lanes) { if (device->lanes > dsi->num_data_lanes) {
@ -1131,7 +1132,8 @@ static int rzg2l_mipi_dsi_host_attach(struct mipi_dsi_host *host,
return -EINVAL; return -EINVAL;
} }
switch (mipi_dsi_pixel_format_to_bpp(device->format)) { bpp = mipi_dsi_pixel_format_to_bpp(device->format);
switch (bpp) {
case 24: case 24:
break; break;
case 18: case 18:
@ -1162,6 +1164,18 @@ static int rzg2l_mipi_dsi_host_attach(struct mipi_dsi_host *host,
drm_bridge_add(&dsi->bridge); drm_bridge_add(&dsi->bridge);
/*
* Report the required division ratio setting for the MIPI clock dividers.
*
* vclk * bpp = hsclk * 8 * num_lanes
*
* vclk * DSI_AB_divider = hsclk * 16
*
* which simplifies to...
* DSI_AB_divider = bpp * 2 / num_lanes
*/
rzg2l_cpg_dsi_div_set_divider(bpp * 2 / dsi->lanes, PLL5_TARGET_DSI);
return 0; return 0;
} }