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drm/msm/dpu: handle pipes as array
There are 2 pipes in a drm plane at most currently, while 4 pipes are required for quad-pipe case. Generalize the handling to pipe pair and ease handling to another pipe pair later. Store pipes in array with removing dedicated r_pipe. Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/675406/ Link: https://lore.kernel.org/r/20250918-v6-16-rc2-quad-pipe-upstream-4-v16-4-ff6232e3472f@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
This commit is contained in:
Jun Nie
Dmitry Baryshkov
parent
2c94547e0c
commit
fb4c972b63
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@ -449,7 +449,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
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struct dpu_plane_state *pstate = NULL;
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const struct msm_format *format;
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struct dpu_hw_ctl *ctl = mixer->lm_ctl;
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u32 lm_idx;
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u32 lm_idx, i;
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bool bg_alpha_enable = false;
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DECLARE_BITMAP(active_fetch, SSPP_MAX);
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DECLARE_BITMAP(active_pipes, SSPP_MAX);
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@ -472,22 +472,17 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
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if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
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bg_alpha_enable = true;
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set_bit(pstate->pipe.sspp->idx, active_fetch);
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set_bit(pstate->pipe.sspp->idx, active_pipes);
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_dpu_crtc_blend_setup_pipe(crtc, plane,
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mixer, cstate->num_mixers,
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pstate->stage,
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format, fb ? fb->modifier : 0,
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&pstate->pipe, 0, stage_cfg);
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if (pstate->r_pipe.sspp) {
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set_bit(pstate->r_pipe.sspp->idx, active_fetch);
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set_bit(pstate->r_pipe.sspp->idx, active_pipes);
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for (i = 0; i < PIPES_PER_STAGE; i++) {
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if (!pstate->pipe[i].sspp)
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continue;
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set_bit(pstate->pipe[i].sspp->idx, active_fetch);
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set_bit(pstate->pipe[i].sspp->idx, active_pipes);
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_dpu_crtc_blend_setup_pipe(crtc, plane,
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mixer, cstate->num_mixers,
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pstate->stage,
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format, fb ? fb->modifier : 0,
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&pstate->r_pipe, 1, stage_cfg);
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&pstate->pipe[i], i, stage_cfg);
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}
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/* blend config update */
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@ -1682,15 +1677,15 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
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seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n",
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state->crtc_x, state->crtc_y, state->crtc_w,
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state->crtc_h);
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seq_printf(s, "\tsspp[0]:%s\n",
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pstate->pipe.sspp->cap->name);
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seq_printf(s, "\tmultirect[0]: mode: %d index: %d\n",
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pstate->pipe.multirect_mode, pstate->pipe.multirect_index);
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if (pstate->r_pipe.sspp) {
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seq_printf(s, "\tsspp[1]:%s\n",
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pstate->r_pipe.sspp->cap->name);
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seq_printf(s, "\tmultirect[1]: mode: %d index: %d\n",
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pstate->r_pipe.multirect_mode, pstate->r_pipe.multirect_index);
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for (i = 0; i < PIPES_PER_STAGE; i++) {
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if (!pstate->pipe[i].sspp)
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continue;
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seq_printf(s, "\tsspp[%d]:%s\n",
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i, pstate->pipe[i].sspp->cap->name);
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seq_printf(s, "\tmultirect[%d]: mode: %d index: %d\n",
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i, pstate->pipe[i].multirect_mode,
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pstate->pipe[i].multirect_index);
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}
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seq_puts(s, "\n");
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@ -622,6 +622,7 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
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struct msm_drm_private *priv = plane->dev->dev_private;
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struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
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u32 fill_color = (color & 0xFFFFFF) | ((alpha & 0xFF) << 24);
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int i;
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DPU_DEBUG_PLANE(pdpu, "\n");
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@ -635,12 +636,13 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
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return;
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/* update sspp */
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_dpu_plane_color_fill_pipe(pstate, &pstate->pipe, &pstate->pipe_cfg.dst_rect,
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fill_color, fmt);
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if (pstate->r_pipe.sspp)
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_dpu_plane_color_fill_pipe(pstate, &pstate->r_pipe, &pstate->r_pipe_cfg.dst_rect,
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for (i = 0; i < PIPES_PER_STAGE; i++) {
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if (!pstate->pipe[i].sspp)
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continue;
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_dpu_plane_color_fill_pipe(pstate, &pstate->pipe[i],
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&pstate->pipe_cfg[i].dst_rect,
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fill_color, fmt);
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}
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}
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static int dpu_plane_prepare_fb(struct drm_plane *plane,
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@ -822,8 +824,8 @@ static int dpu_plane_atomic_check_nosspp(struct drm_plane *plane,
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struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
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u64 max_mdp_clk_rate = kms->perf.max_core_clk_rate;
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struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state);
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struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
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struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
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struct dpu_sw_pipe_cfg *pipe_cfg;
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struct dpu_sw_pipe_cfg *r_pipe_cfg;
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struct drm_rect fb_rect = { 0 };
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uint32_t max_linewidth;
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@ -848,6 +850,9 @@ static int dpu_plane_atomic_check_nosspp(struct drm_plane *plane,
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return -EINVAL;
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}
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/* move the assignment here, to ease handling to another pairs later */
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pipe_cfg = &pstate->pipe_cfg[0];
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r_pipe_cfg = &pstate->pipe_cfg[1];
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/* state->src is 16.16, src_rect is not */
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drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src);
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@ -963,10 +968,10 @@ static int dpu_plane_atomic_check_sspp(struct drm_plane *plane,
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drm_atomic_get_new_plane_state(state, plane);
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struct dpu_plane *pdpu = to_dpu_plane(plane);
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struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state);
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struct dpu_sw_pipe *pipe = &pstate->pipe;
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struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
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struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
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struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
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struct dpu_sw_pipe *pipe = &pstate->pipe[0];
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struct dpu_sw_pipe *r_pipe = &pstate->pipe[1];
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struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg[0];
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struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->pipe_cfg[1];
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int ret = 0;
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ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg,
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@ -1021,15 +1026,15 @@ static int dpu_plane_try_multirect_shared(struct dpu_plane_state *pstate,
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const struct msm_format *fmt,
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uint32_t max_linewidth)
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{
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struct dpu_sw_pipe *pipe = &pstate->pipe;
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struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
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struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
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struct dpu_sw_pipe *prev_pipe = &prev_adjacent_pstate->pipe;
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struct dpu_sw_pipe_cfg *prev_pipe_cfg = &prev_adjacent_pstate->pipe_cfg;
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struct dpu_sw_pipe *pipe = &pstate->pipe[0];
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struct dpu_sw_pipe *r_pipe = &pstate->pipe[1];
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struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg[0];
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struct dpu_sw_pipe *prev_pipe = &prev_adjacent_pstate->pipe[0];
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struct dpu_sw_pipe_cfg *prev_pipe_cfg = &prev_adjacent_pstate->pipe_cfg[0];
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const struct msm_format *prev_fmt = msm_framebuffer_format(prev_adjacent_pstate->base.fb);
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u16 max_tile_height = 1;
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if (prev_adjacent_pstate->r_pipe.sspp != NULL ||
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if (prev_adjacent_pstate->pipe[1].sspp != NULL ||
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prev_pipe->multirect_mode != DPU_SSPP_MULTIRECT_NONE)
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return false;
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@ -1089,10 +1094,10 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
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struct dpu_plane *pdpu = to_dpu_plane(plane);
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struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state);
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struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
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struct dpu_sw_pipe *pipe = &pstate->pipe;
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struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
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struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
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struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
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struct dpu_sw_pipe *pipe = &pstate->pipe[0];
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struct dpu_sw_pipe *r_pipe = &pstate->pipe[1];
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struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg[0];
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struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->pipe_cfg[1];
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const struct drm_crtc_state *crtc_state = NULL;
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uint32_t max_linewidth = dpu_kms->catalog->caps->max_linewidth;
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@ -1136,7 +1141,7 @@ static int dpu_plane_virtual_atomic_check(struct drm_plane *plane,
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drm_atomic_get_old_plane_state(state, plane);
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struct dpu_plane_state *pstate = to_dpu_plane_state(plane_state);
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struct drm_crtc_state *crtc_state = NULL;
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int ret;
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int ret, i;
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if (IS_ERR(plane_state))
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return PTR_ERR(plane_state);
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@ -1154,8 +1159,8 @@ static int dpu_plane_virtual_atomic_check(struct drm_plane *plane,
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* resources are freed by dpu_crtc_assign_plane_resources(),
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* but clean them here.
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*/
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pstate->pipe.sspp = NULL;
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pstate->r_pipe.sspp = NULL;
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for (i = 0; i < PIPES_PER_STAGE; i++)
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pstate->pipe[i].sspp = NULL;
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return 0;
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}
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@ -1193,6 +1198,7 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc,
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struct dpu_sw_pipe_cfg *pipe_cfg;
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struct dpu_sw_pipe_cfg *r_pipe_cfg;
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const struct msm_format *fmt;
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int i;
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if (plane_state->crtc)
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crtc_state = drm_atomic_get_new_crtc_state(state,
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@ -1201,13 +1207,14 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc,
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pstate = to_dpu_plane_state(plane_state);
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prev_adjacent_pstate = prev_adjacent_plane_state ?
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to_dpu_plane_state(prev_adjacent_plane_state) : NULL;
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pipe = &pstate->pipe;
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r_pipe = &pstate->r_pipe;
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pipe_cfg = &pstate->pipe_cfg;
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r_pipe_cfg = &pstate->r_pipe_cfg;
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pipe->sspp = NULL;
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r_pipe->sspp = NULL;
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pipe = &pstate->pipe[0];
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r_pipe = &pstate->pipe[1];
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pipe_cfg = &pstate->pipe_cfg[0];
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r_pipe_cfg = &pstate->pipe_cfg[1];
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for (i = 0; i < PIPES_PER_STAGE; i++)
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pstate->pipe[i].sspp = NULL;
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if (!plane_state->fb)
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return -EINVAL;
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@ -1318,6 +1325,7 @@ void dpu_plane_flush(struct drm_plane *plane)
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{
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struct dpu_plane *pdpu;
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struct dpu_plane_state *pstate;
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int i;
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if (!plane || !plane->state) {
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DPU_ERROR("invalid plane\n");
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@ -1338,8 +1346,8 @@ void dpu_plane_flush(struct drm_plane *plane)
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/* force 100% alpha */
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_dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
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else {
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dpu_plane_flush_csc(pdpu, &pstate->pipe);
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dpu_plane_flush_csc(pdpu, &pstate->r_pipe);
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for (i = 0; i < PIPES_PER_STAGE; i++)
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dpu_plane_flush_csc(pdpu, &pstate->pipe[i]);
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}
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/* flag h/w flush complete */
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@ -1440,15 +1448,12 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane,
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struct dpu_plane *pdpu = to_dpu_plane(plane);
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struct drm_plane_state *state = plane->state;
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struct dpu_plane_state *pstate = to_dpu_plane_state(state);
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struct dpu_sw_pipe *pipe = &pstate->pipe;
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struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
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struct drm_crtc *crtc = state->crtc;
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struct drm_framebuffer *fb = state->fb;
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bool is_rt_pipe;
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const struct msm_format *fmt =
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msm_framebuffer_format(fb);
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struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
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struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
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int i;
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pstate->pending = true;
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@ -1463,12 +1468,12 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane,
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crtc->base.id, DRM_RECT_ARG(&state->dst),
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&fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt));
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dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt,
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drm_mode_vrefresh(&crtc->mode),
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&pstate->layout);
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if (r_pipe->sspp) {
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dpu_plane_sspp_update_pipe(plane, r_pipe, r_pipe_cfg, fmt,
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/* move the assignment here, to ease handling to another pairs later */
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for (i = 0; i < PIPES_PER_STAGE; i++) {
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if (!drm_rect_width(&pstate->pipe_cfg[i].src_rect))
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continue;
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dpu_plane_sspp_update_pipe(plane, &pstate->pipe[i],
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&pstate->pipe_cfg[i], fmt,
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drm_mode_vrefresh(&crtc->mode),
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&pstate->layout);
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}
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@ -1476,15 +1481,17 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane,
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if (pstate->needs_qos_remap)
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pstate->needs_qos_remap = false;
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pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt,
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&crtc->mode, pipe_cfg);
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pstate->plane_fetch_bw = 0;
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pstate->plane_clk = 0;
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for (i = 0; i < PIPES_PER_STAGE; i++) {
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if (!drm_rect_width(&pstate->pipe_cfg[i].src_rect))
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continue;
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pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt,
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&crtc->mode, &pstate->pipe_cfg[i]);
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pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, pipe_cfg);
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if (r_pipe->sspp) {
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pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, r_pipe_cfg);
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pstate->plane_clk = max(pstate->plane_clk, _dpu_plane_calc_clk(&crtc->mode, r_pipe_cfg));
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pstate->plane_clk = max(pstate->plane_clk,
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_dpu_plane_calc_clk(&crtc->mode,
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&pstate->pipe_cfg[i]));
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}
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}
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@ -1492,17 +1499,28 @@ static void _dpu_plane_atomic_disable(struct drm_plane *plane)
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{
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struct drm_plane_state *state = plane->state;
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struct dpu_plane_state *pstate = to_dpu_plane_state(state);
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struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
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struct dpu_sw_pipe *pipe;
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int i;
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trace_dpu_plane_disable(DRMID(plane), false,
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pstate->pipe.multirect_mode);
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for (i = 0; i < PIPES_PER_STAGE; i += 1) {
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pipe = &pstate->pipe[i];
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if (!pipe->sspp)
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continue;
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if (r_pipe->sspp) {
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r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
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r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
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trace_dpu_plane_disable(DRMID(plane), false,
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pstate->pipe[i].multirect_mode);
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if (r_pipe->sspp->ops.setup_multirect)
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r_pipe->sspp->ops.setup_multirect(r_pipe);
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if (i % PIPES_PER_STAGE == 0)
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continue;
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/*
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* clear multirect for the right pipe so that the SSPP
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* can be further reused in the solo mode
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*/
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pipe->multirect_index = DPU_SSPP_RECT_SOLO;
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pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
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if (pipe->sspp->ops.setup_multirect)
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pipe->sspp->ops.setup_multirect(pipe);
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}
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pstate->pending = true;
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@ -1597,31 +1615,26 @@ static void dpu_plane_atomic_print_state(struct drm_printer *p,
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const struct drm_plane_state *state)
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{
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const struct dpu_plane_state *pstate = to_dpu_plane_state(state);
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const struct dpu_sw_pipe *pipe = &pstate->pipe;
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const struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
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const struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
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const struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
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const struct dpu_sw_pipe *pipe;
|
||||
const struct dpu_sw_pipe_cfg *pipe_cfg;
|
||||
int i;
|
||||
|
||||
drm_printf(p, "\tstage=%d\n", pstate->stage);
|
||||
|
||||
if (pipe->sspp) {
|
||||
drm_printf(p, "\tsspp[0]=%s\n", pipe->sspp->cap->name);
|
||||
drm_printf(p, "\tmultirect_mode[0]=%s\n",
|
||||
for (i = 0; i < PIPES_PER_STAGE; i++) {
|
||||
pipe = &pstate->pipe[i];
|
||||
if (!pipe->sspp)
|
||||
continue;
|
||||
pipe_cfg = &pstate->pipe_cfg[i];
|
||||
drm_printf(p, "\tsspp[%d]=%s\n", i, pipe->sspp->cap->name);
|
||||
drm_printf(p, "\tmultirect_mode[%d]=%s\n", i,
|
||||
dpu_get_multirect_mode(pipe->multirect_mode));
|
||||
drm_printf(p, "\tmultirect_index[0]=%s\n",
|
||||
drm_printf(p, "\tmultirect_index[%d]=%s\n", i,
|
||||
dpu_get_multirect_index(pipe->multirect_index));
|
||||
drm_printf(p, "\tsrc[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->src_rect));
|
||||
drm_printf(p, "\tdst[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->dst_rect));
|
||||
}
|
||||
|
||||
if (r_pipe->sspp) {
|
||||
drm_printf(p, "\tsspp[1]=%s\n", r_pipe->sspp->cap->name);
|
||||
drm_printf(p, "\tmultirect_mode[1]=%s\n",
|
||||
dpu_get_multirect_mode(r_pipe->multirect_mode));
|
||||
drm_printf(p, "\tmultirect_index[1]=%s\n",
|
||||
dpu_get_multirect_index(r_pipe->multirect_index));
|
||||
drm_printf(p, "\tsrc[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->src_rect));
|
||||
drm_printf(p, "\tdst[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->dst_rect));
|
||||
drm_printf(p, "\tsrc[%d]=" DRM_RECT_FMT "\n", i,
|
||||
DRM_RECT_ARG(&pipe_cfg->src_rect));
|
||||
drm_printf(p, "\tdst[%d]=" DRM_RECT_FMT "\n", i,
|
||||
DRM_RECT_ARG(&pipe_cfg->dst_rect));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1659,14 +1672,17 @@ void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
|
|||
struct dpu_plane *pdpu = to_dpu_plane(plane);
|
||||
struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
|
||||
struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
|
||||
int i;
|
||||
|
||||
if (!pdpu->is_rt_pipe)
|
||||
return;
|
||||
|
||||
pm_runtime_get_sync(&dpu_kms->pdev->dev);
|
||||
_dpu_plane_set_qos_ctrl(plane, &pstate->pipe, enable);
|
||||
if (pstate->r_pipe.sspp)
|
||||
_dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, enable);
|
||||
for (i = 0; i < PIPES_PER_STAGE; i++) {
|
||||
if (!pstate->pipe[i].sspp)
|
||||
continue;
|
||||
_dpu_plane_set_qos_ctrl(plane, &pstate->pipe[i], enable);
|
||||
}
|
||||
pm_runtime_put_sync(&dpu_kms->pdev->dev);
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -17,10 +17,8 @@
|
|||
/**
|
||||
* struct dpu_plane_state: Define dpu extension of drm plane state object
|
||||
* @base: base drm plane state object
|
||||
* @pipe: software pipe description
|
||||
* @r_pipe: software pipe description of the second pipe
|
||||
* @pipe_cfg: software pipe configuration
|
||||
* @r_pipe_cfg: software pipe configuration for the second pipe
|
||||
* @pipe: software pipe description array
|
||||
* @pipe_cfg: software pipe configuration array
|
||||
* @stage: assigned by crtc blender
|
||||
* @needs_qos_remap: qos remap settings need to be updated
|
||||
* @multirect_index: index of the rectangle of SSPP
|
||||
|
|
@ -33,10 +31,8 @@
|
|||
*/
|
||||
struct dpu_plane_state {
|
||||
struct drm_plane_state base;
|
||||
struct dpu_sw_pipe pipe;
|
||||
struct dpu_sw_pipe r_pipe;
|
||||
struct dpu_sw_pipe_cfg pipe_cfg;
|
||||
struct dpu_sw_pipe_cfg r_pipe_cfg;
|
||||
struct dpu_sw_pipe pipe[PIPES_PER_STAGE];
|
||||
struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_STAGE];
|
||||
enum dpu_stage stage;
|
||||
bool needs_qos_remap;
|
||||
bool pending;
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user