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drm/amdgpu/mes11: move pipe reset to mes use_mmio patch
This makes the code flows cleaner and it's only supported on the use_mmio path. v2: fix typo v3: fix typo v4: directly clear ACTIVE and DEQUEUE_REQUEST (Shaoyun Liu) Reviewed-by: Jesse Zhang <jesse.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
2c476a67c6
commit
fb1d4b2112
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@ -6814,69 +6814,6 @@ static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring)
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amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
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}
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static bool gfx_v11_pipe_reset_support(struct amdgpu_device *adev)
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{
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/* Disable the pipe reset until the CPFW fully support it.*/
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dev_warn_once(adev->dev, "The CPFW hasn't support pipe reset yet.\n");
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return false;
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}
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static int gfx_v11_reset_gfx_pipe(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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uint32_t reset_pipe = 0, clean_pipe = 0;
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int r;
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if (!gfx_v11_pipe_reset_support(adev))
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return -EOPNOTSUPP;
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gfx_v11_0_set_safe_mode(adev, 0);
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mutex_lock(&adev->srbm_mutex);
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soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
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switch (ring->pipe) {
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case 0:
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reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,
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PFP_PIPE0_RESET, 1);
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reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,
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ME_PIPE0_RESET, 1);
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clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,
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PFP_PIPE0_RESET, 0);
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clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,
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ME_PIPE0_RESET, 0);
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break;
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case 1:
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reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,
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PFP_PIPE1_RESET, 1);
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reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,
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ME_PIPE1_RESET, 1);
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clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,
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PFP_PIPE1_RESET, 0);
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clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,
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ME_PIPE1_RESET, 0);
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break;
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default:
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break;
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}
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WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe);
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WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe);
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r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) -
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RS64_FW_UC_START_ADDR_LO;
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soc21_grbm_select(adev, 0, 0, 0, 0);
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mutex_unlock(&adev->srbm_mutex);
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gfx_v11_0_unset_safe_mode(adev, 0);
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dev_info(adev->dev, "The ring %s pipe reset to the ME firmware start PC: %s\n", ring->name,
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r == 0 ? "successfully" : "failed");
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/* FIXME: Sometimes driver can't cache the ME firmware start PC correctly,
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* so the pipe reset status relies on the later gfx ring test result.
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*/
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return 0;
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}
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static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring,
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unsigned int vmid,
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struct amdgpu_fence *timedout_fence)
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@ -6888,13 +6825,8 @@ static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring,
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amdgpu_ring_reset_helper_begin(ring, timedout_fence);
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r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, use_mmio, 0);
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if (r) {
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dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r);
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r = gfx_v11_reset_gfx_pipe(ring);
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if (r)
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return r;
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}
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if (r)
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return r;
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if (use_mmio) {
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r = gfx_v11_0_kgq_init_queue(ring, true);
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@ -6913,158 +6845,6 @@ static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring,
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return amdgpu_ring_reset_helper_end(ring, timedout_fence);
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}
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/*
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* With MEC pipe reset asserted, clear CP_HQD_ACTIVE / CP_HQD_DEQUEUE_REQUEST for
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* every queue on (me, pipe). HQDs must be torn down while pipe reset stays
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* asserted; only then clear the pipe reset bit.
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* Caller must hold adev->srbm_mutex.
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*/
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static void gfx_v11_0_clear_hqds_on_mec_pipe(struct amdgpu_device *adev, u32 me,
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u32 pipe)
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{
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unsigned int q;
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for (q = 0; q < adev->gfx.mec.num_queue_per_pipe; q++) {
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soc21_grbm_select(adev, me, pipe, q, 0);
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/* Start from a clean HQD dequeue state before forcing HQD inactive. */
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WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0);
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WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0);
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}
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}
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static int gfx_v11_0_reset_compute_pipe(struct amdgpu_device *adev,
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u32 me, u32 pipe, u32 queue)
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{
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uint32_t reset_val, clean_val;
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int r;
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if (!gfx_v11_pipe_reset_support(adev))
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return -EOPNOTSUPP;
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gfx_v11_0_set_safe_mode(adev, 0);
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mutex_lock(&adev->srbm_mutex);
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soc21_grbm_select(adev, me, pipe, queue, 0);
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if (adev->gfx.rs64_enable) {
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reset_val = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
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clean_val = reset_val;
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switch (pipe) {
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case 0:
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reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL,
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MEC_PIPE0_RESET, 1);
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clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL,
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MEC_PIPE0_RESET, 0);
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break;
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case 1:
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reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL,
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MEC_PIPE1_RESET, 1);
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clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL,
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MEC_PIPE1_RESET, 0);
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break;
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case 2:
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reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL,
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MEC_PIPE2_RESET, 1);
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clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL,
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MEC_PIPE2_RESET, 0);
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break;
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case 3:
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reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL,
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MEC_PIPE3_RESET, 1);
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clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL,
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MEC_PIPE3_RESET, 0);
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break;
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default:
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break;
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}
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WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_val);
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gfx_v11_0_clear_hqds_on_mec_pipe(adev, me, pipe);
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WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_val);
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r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) -
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RS64_FW_UC_START_ADDR_LO;
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} else {
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reset_val = RREG32_SOC15(GC, 0, regCP_MEC_CNTL);
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clean_val = reset_val;
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if (me == 1) {
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switch (pipe) {
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case 0:
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reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL,
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MEC_ME1_PIPE0_RESET, 1);
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clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL,
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MEC_ME1_PIPE0_RESET, 0);
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break;
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case 1:
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reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL,
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MEC_ME1_PIPE1_RESET, 1);
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clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL,
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MEC_ME1_PIPE1_RESET, 0);
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break;
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case 2:
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reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL,
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MEC_ME1_PIPE2_RESET, 1);
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clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL,
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MEC_ME1_PIPE2_RESET, 0);
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break;
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case 3:
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reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL,
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MEC_ME1_PIPE3_RESET, 1);
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clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL,
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MEC_ME1_PIPE3_RESET, 0);
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break;
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default:
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break;
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}
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/* mec1 fw pc: CP_MEC1_INSTR_PNTR */
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} else {
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switch (pipe) {
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case 0:
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reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL,
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MEC_ME2_PIPE0_RESET, 1);
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clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL,
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MEC_ME2_PIPE0_RESET, 0);
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break;
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case 1:
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reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL,
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MEC_ME2_PIPE1_RESET, 1);
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clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL,
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MEC_ME2_PIPE1_RESET, 0);
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break;
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case 2:
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reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL,
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MEC_ME2_PIPE2_RESET, 1);
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clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL,
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MEC_ME2_PIPE2_RESET, 0);
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break;
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case 3:
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reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL,
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MEC_ME2_PIPE3_RESET, 1);
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clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL,
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MEC_ME2_PIPE3_RESET, 0);
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break;
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default:
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break;
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}
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/* mec2 fw pc: CP:CP_MEC2_INSTR_PNTR */
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}
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WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_val);
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gfx_v11_0_clear_hqds_on_mec_pipe(adev, me, pipe);
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WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_val);
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r = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_MEC1_INSTR_PNTR));
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}
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soc21_grbm_select(adev, 0, 0, 0, 0);
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mutex_unlock(&adev->srbm_mutex);
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gfx_v11_0_unset_safe_mode(adev, 0);
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dev_dbg(adev->dev, "MEC pipe me%u pipe%u queue%u resets to MEC FW start PC: %s\n",
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me, pipe, queue, r == 0 ? "successfully" : "failed");
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/*FIXME:Sometimes driver can't cache the MEC firmware start PC correctly, so the pipe
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* reset status relies on the compute ring test result.
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*/
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return 0;
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}
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static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring,
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unsigned int vmid,
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struct amdgpu_fence *timedout_fence)
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@ -7076,12 +6856,8 @@ static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring,
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amdgpu_ring_reset_helper_begin(ring, timedout_fence);
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r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, use_mmio, 0);
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if (r) {
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dev_warn(adev->dev, "fail(%d) to reset kcq and try pipe reset\n", r);
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r = gfx_v11_0_reset_compute_pipe(adev, ring->me, ring->pipe, ring->queue);
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if (r)
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return r;
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}
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if (r)
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return r;
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if (use_mmio) {
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r = gfx_v11_0_kcq_init_queue(ring, true);
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@ -392,6 +392,233 @@ static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes,
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offsetof(union MESAPI__REMOVE_QUEUE, api_status));
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}
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static bool mes_v11_0_pipe_reset_support(struct amdgpu_device *adev)
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{
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/* Disable the pipe reset until the CPFW fully support it.*/
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dev_warn_once(adev->dev, "The CPFW hasn't support pipe reset yet.\n");
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return false;
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}
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static int mes_v11_0_reset_gfx_pipe_mmio(struct amdgpu_device *adev,
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u32 me, u32 pipe, u32 queue)
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{
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uint32_t reset_pipe = 0, clean_pipe = 0;
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int r;
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if (!mes_v11_0_pipe_reset_support(adev))
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return -EOPNOTSUPP;
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amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
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mutex_lock(&adev->srbm_mutex);
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soc21_grbm_select(adev, me, pipe, queue, 0);
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switch (pipe) {
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case 0:
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reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,
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PFP_PIPE0_RESET, 1);
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reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,
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ME_PIPE0_RESET, 1);
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clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,
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PFP_PIPE0_RESET, 0);
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clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,
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ME_PIPE0_RESET, 0);
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break;
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case 1:
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reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,
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PFP_PIPE1_RESET, 1);
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reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,
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ME_PIPE1_RESET, 1);
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clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,
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PFP_PIPE1_RESET, 0);
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clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,
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ME_PIPE1_RESET, 0);
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break;
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default:
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break;
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}
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WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe);
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WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe);
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r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) -
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RS64_FW_UC_START_ADDR_LO;
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soc21_grbm_select(adev, 0, 0, 0, 0);
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mutex_unlock(&adev->srbm_mutex);
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amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
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dev_info(adev->dev, "The gfx pipe reset to the ME firmware start PC: %s\n",
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r == 0 ? "successfully" : "failed");
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/* FIXME: Sometimes driver can't cache the ME firmware start PC correctly,
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* so the pipe reset status relies on the later gfx ring test result.
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*/
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return 0;
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}
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/*
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* With MEC pipe reset asserted, clear CP_HQD_ACTIVE / CP_HQD_DEQUEUE_REQUEST for
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* every queue on (me, pipe). HQDs must be torn down while pipe reset stays
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* asserted; only then clear the pipe reset bit.
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* Caller must hold adev->srbm_mutex.
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*/
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static void mes_v11_0_clear_hqds_on_mec_pipe(struct amdgpu_device *adev, u32 me,
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u32 pipe)
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{
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unsigned int q;
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for (q = 0; q < adev->gfx.mec.num_queue_per_pipe; q++) {
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soc21_grbm_select(adev, me, pipe, q, 0);
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/* Start from a clean HQD dequeue state before forcing HQD inactive. */
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WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0);
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WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0);
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}
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}
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static int mes_v11_0_reset_compute_pipe_mmio(struct amdgpu_device *adev,
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u32 me, u32 pipe, u32 queue)
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{
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uint32_t reset_val, clean_val;
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int r;
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if (!mes_v11_0_pipe_reset_support(adev))
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return -EOPNOTSUPP;
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amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
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mutex_lock(&adev->srbm_mutex);
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soc21_grbm_select(adev, me, pipe, queue, 0);
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if (adev->gfx.rs64_enable) {
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reset_val = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
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clean_val = reset_val;
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switch (pipe) {
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case 0:
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reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL,
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MEC_PIPE0_RESET, 1);
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clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL,
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MEC_PIPE0_RESET, 0);
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break;
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case 1:
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reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL,
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MEC_PIPE1_RESET, 1);
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clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL,
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MEC_PIPE1_RESET, 0);
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break;
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case 2:
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reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL,
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MEC_PIPE2_RESET, 1);
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clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL,
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MEC_PIPE2_RESET, 0);
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break;
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case 3:
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reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL,
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MEC_PIPE3_RESET, 1);
|
||||
clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL,
|
||||
MEC_PIPE3_RESET, 0);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_val);
|
||||
mes_v11_0_clear_hqds_on_mec_pipe(adev, me, pipe);
|
||||
WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_val);
|
||||
r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) -
|
||||
RS64_FW_UC_START_ADDR_LO;
|
||||
} else {
|
||||
reset_val = RREG32_SOC15(GC, 0, regCP_MEC_CNTL);
|
||||
clean_val = reset_val;
|
||||
|
||||
if (me == 1) {
|
||||
switch (pipe) {
|
||||
case 0:
|
||||
reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL,
|
||||
MEC_ME1_PIPE0_RESET, 1);
|
||||
clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL,
|
||||
MEC_ME1_PIPE0_RESET, 0);
|
||||
break;
|
||||
case 1:
|
||||
reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL,
|
||||
MEC_ME1_PIPE1_RESET, 1);
|
||||
clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL,
|
||||
MEC_ME1_PIPE1_RESET, 0);
|
||||
break;
|
||||
case 2:
|
||||
reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL,
|
||||
MEC_ME1_PIPE2_RESET, 1);
|
||||
clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL,
|
||||
MEC_ME1_PIPE2_RESET, 0);
|
||||
break;
|
||||
case 3:
|
||||
reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL,
|
||||
MEC_ME1_PIPE3_RESET, 1);
|
||||
clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL,
|
||||
MEC_ME1_PIPE3_RESET, 0);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
/* mec1 fw pc: CP_MEC1_INSTR_PNTR */
|
||||
} else {
|
||||
switch (pipe) {
|
||||
case 0:
|
||||
reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL,
|
||||
MEC_ME2_PIPE0_RESET, 1);
|
||||
clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL,
|
||||
MEC_ME2_PIPE0_RESET, 0);
|
||||
break;
|
||||
case 1:
|
||||
reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL,
|
||||
MEC_ME2_PIPE1_RESET, 1);
|
||||
clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL,
|
||||
MEC_ME2_PIPE1_RESET, 0);
|
||||
break;
|
||||
case 2:
|
||||
reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL,
|
||||
MEC_ME2_PIPE2_RESET, 1);
|
||||
clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL,
|
||||
MEC_ME2_PIPE2_RESET, 0);
|
||||
break;
|
||||
case 3:
|
||||
reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL,
|
||||
MEC_ME2_PIPE3_RESET, 1);
|
||||
clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL,
|
||||
MEC_ME2_PIPE3_RESET, 0);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
/* mec2 fw pc: CP:CP_MEC2_INSTR_PNTR */
|
||||
}
|
||||
WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_val);
|
||||
mes_v11_0_clear_hqds_on_mec_pipe(adev, me, pipe);
|
||||
WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_val);
|
||||
r = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_MEC1_INSTR_PNTR));
|
||||
}
|
||||
|
||||
soc21_grbm_select(adev, 0, 0, 0, 0);
|
||||
mutex_unlock(&adev->srbm_mutex);
|
||||
amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
|
||||
|
||||
dev_dbg(adev->dev, "MEC pipe me%u pipe%u queue%u resets to MEC FW start PC: %s\n",
|
||||
me, pipe, queue, r == 0 ? "successfully" : "failed");
|
||||
/*FIXME:Sometimes driver can't cache the MEC firmware start PC correctly, so the pipe
|
||||
* reset status relies on the compute ring test result.
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mes_v11_0_reset_pipe_mmio(struct amdgpu_mes *mes, uint32_t queue_type,
|
||||
uint32_t me_id, uint32_t pipe_id,
|
||||
uint32_t queue_id, uint32_t vmid)
|
||||
{
|
||||
struct amdgpu_device *adev = mes->adev;
|
||||
|
||||
if (queue_type == AMDGPU_RING_TYPE_GFX)
|
||||
return mes_v11_0_reset_gfx_pipe_mmio(adev, me_id, pipe_id, queue_id);
|
||||
else if (queue_type == AMDGPU_RING_TYPE_COMPUTE)
|
||||
return mes_v11_0_reset_compute_pipe_mmio(adev, me_id, pipe_id, queue_id);
|
||||
else
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type,
|
||||
uint32_t me_id, uint32_t pipe_id,
|
||||
uint32_t queue_id, uint32_t vmid)
|
||||
|
|
@ -764,10 +991,16 @@ static int mes_v11_0_reset_hw_queue(struct amdgpu_mes *mes,
|
|||
{
|
||||
union MESAPI__RESET mes_reset_queue_pkt;
|
||||
|
||||
if (input->use_mmio)
|
||||
return mes_v11_0_reset_queue_mmio(mes, input->queue_type,
|
||||
input->me_id, input->pipe_id,
|
||||
input->queue_id, input->vmid);
|
||||
if (input->use_mmio) {
|
||||
int r = mes_v11_0_reset_queue_mmio(mes, input->queue_type,
|
||||
input->me_id, input->pipe_id,
|
||||
input->queue_id, input->vmid);
|
||||
if (r)
|
||||
return mes_v11_0_reset_pipe_mmio(mes, input->queue_type,
|
||||
input->me_id, input->pipe_id,
|
||||
input->queue_id, input->vmid);
|
||||
return 0;
|
||||
}
|
||||
|
||||
memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt));
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user