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arm64: dts: qcom: monaco: add dt entry for lpass lpi pinctrl

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Add LPASS LPI pinctrl node used for setting MI2S and soundwire pin
configs.

Co-developed-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260313103824.2634519-4-srinivas.kandagatla@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Srinivas Kandagatla 2026-03-13 10:38:18 +00:00 committed by Bjorn Andersson
parent 2f5a32f448
commit faf08fd434
1 changed files with 15 additions and 0 deletions
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15
arch/arm64/boot/dts/qcom/monaco.dtsi
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@ -21,6 +21,7 @@
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@ -2872,6 +2873,20 @@ q6prmcc: clock-controller {
};
};
lpass_tlmm: pinctrl@3440000 {
compatible = "qcom,qcs8300-lpass-lpi-pinctrl", "qcom,sm8450-lpass-lpi-pinctrl";
reg = <0x0 0x03440000 0x0 0x20000>,
<0x0 0x034d0000 0x0 0x10000>;
clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "core", "audio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpass_tlmm 0 0 23>;
};
lpass_ag_noc: interconnect@3c40000 {
compatible = "qcom,qcs8300-lpass-ag-noc";
reg = <0x0 0x03c40000 0x0 0x17200>;