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dt-bindings: PCI: renesas,r9a08g045s33-pcie: Document RZ/G3E SoC
Extend the existing device tree bindings for Renesas RZ/G3S PCIe controller to include support for the RZ/G3E (renesas,r9a09g047e57-pcie) PCIe controller. The RZ/G3E PCIe controller is similar to RZ/G3S but has some key differences: - Uses a different device ID - Supports PCIe Gen3 (8.0 GT/s) link speeds - Uses a different clock naming (clkpmu vs clkl1pm) - Has a different set of interrupts, interrupt ordering, and reset signals Add device tree bindings for renesas,r9a09g047e57-pcie compatible IPs. Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> # RZ/V2N EVK Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://patch.msgid.link/20260306143423.19562-7-john.madieu.xa@bp.renesas.com
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@ -10,17 +10,21 @@ maintainers:
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- Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
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description:
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Renesas RZ/G3S PCIe host controller complies with PCIe Base Specification
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4.0 and supports up to 5 GT/s (Gen2).
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Renesas RZ/G3{E,S} PCIe host controllers comply with PCIe
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Base Specification 4.0 and support up to 5 GT/s (Gen2) for RZ/G3S and
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up to 8 GT/s (Gen3) for RZ/G3E.
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properties:
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compatible:
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const: renesas,r9a08g045-pcie # RZ/G3S
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enum:
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- renesas,r9a08g045-pcie # RZ/G3S
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- renesas,r9a09g047-pcie # RZ/G3E
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reg:
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maxItems: 1
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interrupts:
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minItems: 16
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items:
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- description: System error interrupt
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- description: System error on correctable error interrupt
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@ -38,8 +42,16 @@ properties:
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- description: PCIe event interrupt
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- description: Message interrupt
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- description: All interrupts
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- description: Link equalization request interrupt
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- description: Turn off event interrupt
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- description: PMU power off interrupt
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- description: D3 event function 0 interrupt
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- description: D3 event function 1 interrupt
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- description: Configuration PMCSR write clear function 0 interrupt
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- description: Configuration PMCSR write clear function 1 interrupt
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interrupt-names:
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minItems: 16
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items:
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- const: serr
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- const: serr_cor
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@ -57,20 +69,28 @@ properties:
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- const: pcie_evt
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- const: msg
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- const: all
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- const: link_equalization_request
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- const: turn_off_event
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- const: pmu_poweroff
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- const: d3_event_f0
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- const: d3_event_f1
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- const: cfg_pmcsr_writeclear_f0
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- const: cfg_pmcsr_writeclear_f1
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interrupt-controller: true
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clocks:
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items:
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- description: System clock
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- description: PM control clock
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- description: PM control clock or clock for L1 substate handling
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clock-names:
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items:
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- const: aclk
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- const: pm
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- enum: [pm, pmu]
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resets:
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minItems: 1
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items:
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- description: AXI2PCIe Bridge reset
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- description: Data link layer/transaction layer reset
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@ -81,6 +101,7 @@ properties:
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- description: Configuration register reset
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reset-names:
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minItems: 1
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items:
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- const: aresetn
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- const: rst_b
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@ -128,7 +149,9 @@ patternProperties:
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const: 0x1912
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device-id:
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const: 0x0033
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enum:
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- 0x0033
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- 0x0039
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clocks:
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items:
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@ -167,6 +190,44 @@ required:
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allOf:
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- $ref: /schemas/pci/pci-host-bridge.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r9a08g045-pcie
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then:
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properties:
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interrupts:
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maxItems: 16
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interrupt-names:
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maxItems: 16
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clock-names:
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items:
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- const: aclk
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- const: pm
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resets:
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minItems: 7
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reset-names:
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minItems: 7
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r9a09g047-pcie
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then:
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properties:
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interrupts:
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minItems: 23
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interrupt-names:
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minItems: 23
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clock-names:
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items:
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- const: aclk
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- const: pmu
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resets:
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maxItems: 1
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reset-names:
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maxItems: 1
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unevaluatedProperties: false
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