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drm/i915/dsb: Use non-locked register access

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Avoid the locking overhead for DSB registers. We don't need the locks
and intel_dsb_commit() in particular needs to be called from the
vblank evade critical section and thus needs to be fast.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230606191504.18099-3-ville.syrjala@linux.intel.com
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
This commit is contained in:
Ville Syrjälä 2023-06-06 22:14:47 +03:00
parent f067976e49
commit fa1b97f85d
1 changed files with 9 additions and 9 deletions
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18
drivers/gpu/drm/i915/display/intel_dsb.c
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@ -112,7 +112,7 @@ static void intel_dsb_dump(struct intel_dsb *dsb)
static bool is_dsb_busy(struct drm_i915_private *i915, enum pipe pipe,
enum dsb_id id)
{
return intel_de_read(i915, DSB_CTRL(pipe, id)) & DSB_STATUS_BUSY;
return intel_de_read_fw(i915, DSB_CTRL(pipe, id)) & DSB_STATUS_BUSY;
}
static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw)
@ -273,13 +273,13 @@ void intel_dsb_commit(struct intel_dsb *dsb, bool wait_for_vblank)
return;
}
intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id),
(wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0) |
DSB_ENABLE);
intel_de_write(dev_priv, DSB_HEAD(pipe, dsb->id),
i915_ggtt_offset(dsb->vma));
intel_de_write(dev_priv, DSB_TAIL(pipe, dsb->id),
i915_ggtt_offset(dsb->vma) + tail);
intel_de_write_fw(dev_priv, DSB_CTRL(pipe, dsb->id),
(wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0) |
DSB_ENABLE);
intel_de_write_fw(dev_priv, DSB_HEAD(pipe, dsb->id),
i915_ggtt_offset(dsb->vma));
intel_de_write_fw(dev_priv, DSB_TAIL(pipe, dsb->id),
i915_ggtt_offset(dsb->vma) + tail);
}
void intel_dsb_wait(struct intel_dsb *dsb)
@ -307,7 +307,7 @@ void intel_dsb_wait(struct intel_dsb *dsb)
/* Attempt to reset it */
dsb->free_pos = 0;
dsb->ins_start_offset = 0;
intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id), 0);
intel_de_write_fw(dev_priv, DSB_CTRL(pipe, dsb->id), 0);
}
/**