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PCI: dwc: Update pci->num_lanes to maximum supported link width
If the num-lanes property is not present in the devicetree, update pci->num_lanes with the hardware supported maximum link width using the newly introduced dw_pcie_link_get_max_link_width() API. The API is used to get the Maximum Link Width (MLW) of the controller. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> [mani: reworded commit message a bit] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://patch.msgid.link/20250328-preset_v6-v9-3-22cfa0490518@oss.qualcomm.com
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@ -523,6 +523,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
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dw_pcie_iatu_detect(pci);
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if (pci->num_lanes < 1)
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pci->num_lanes = dw_pcie_link_get_max_link_width(pci);
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/*
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* Allocate the resource for MSG TLP before programming the iATU
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* outbound window in dw_pcie_setup_rc(). Since the allocation depends
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@ -781,6 +781,14 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci)
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}
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int dw_pcie_link_get_max_link_width(struct dw_pcie *pci)
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{
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u8 cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
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u32 lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);
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return FIELD_GET(PCI_EXP_LNKCAP_MLW, lnkcap);
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}
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static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
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{
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u32 lnkcap, lwsc, plc;
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@ -540,6 +540,7 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val);
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int dw_pcie_link_up(struct dw_pcie *pci);
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void dw_pcie_upconfig_setup(struct dw_pcie *pci);
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int dw_pcie_wait_for_link(struct dw_pcie *pci);
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int dw_pcie_link_get_max_link_width(struct dw_pcie *pci);
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int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
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const struct dw_pcie_ob_atu_cfg *atu);
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int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,
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