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ASoC: ab8500: Correct digital interface format setup
The codec programs I2S as an undelayed left-aligned format, although the
hardware manual defines delayed left-aligned as I2S compatible. It also
enables the master generator when the codec is a clock consumer, changes
registers before the complete format has been validated, and discards
register I/O errors.
Build all three interface register values before writing them, use the
required one-bit I2S delay, only run the master generator for a provider
configuration, and propagate write failures.
Fixes: 679d7abdc7 ("ASoC: codecs: Add AB8500 codec-driver")
Assisted-by: LLM
Signed-off-by: Linus Walleij <linusw@kernel.org>
Link: https://patch.msgid.link/20260831-ab8500-codec-fixes-v1-3-f85024e717e3@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Linus Walleij
Mark Brown
parent
103fe1a37f
commit
f98785adf0
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@ -1737,149 +1737,91 @@ static int ab8500_audio_set_ear_cmv(struct snd_soc_component *component,
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return 0;
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}
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static int ab8500_audio_set_bit_delay(struct snd_soc_dai *dai,
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unsigned int delay)
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{
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unsigned int mask, val;
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struct snd_soc_component *component = dai->component;
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mask = BIT(AB8500_DIGIFCONF2_IF0DEL);
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val = 0;
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switch (delay) {
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case 0:
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break;
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case 1:
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val |= BIT(AB8500_DIGIFCONF2_IF0DEL);
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break;
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default:
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dev_err(dai->component->dev,
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"%s: ERROR: Unsupported bit-delay (0x%x)!\n",
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__func__, delay);
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return -EINVAL;
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}
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dev_dbg(dai->component->dev, "%s: IF0 Bit-delay: %d bits.\n",
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__func__, delay);
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snd_soc_component_update_bits(component, AB8500_DIGIFCONF2, mask, val);
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return 0;
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}
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/* Gates clocking according format mask */
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static int ab8500_codec_set_dai_clock_gate(struct snd_soc_component *component,
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unsigned int fmt)
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{
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unsigned int mask;
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unsigned int val;
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mask = BIT(AB8500_DIGIFCONF1_ENMASTGEN) |
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BIT(AB8500_DIGIFCONF1_ENFSBITCLK0);
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val = BIT(AB8500_DIGIFCONF1_ENMASTGEN);
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switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
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case SND_SOC_DAIFMT_CONT: /* continuous clock */
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dev_dbg(component->dev, "%s: IF0 Clock is continuous.\n",
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__func__);
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val |= BIT(AB8500_DIGIFCONF1_ENFSBITCLK0);
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break;
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case SND_SOC_DAIFMT_GATED: /* clock is gated */
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dev_dbg(component->dev, "%s: IF0 Clock is gated.\n",
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__func__);
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break;
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default:
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dev_err(component->dev,
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"%s: ERROR: Unsupported clock mask (0x%x)!\n",
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__func__, fmt & SND_SOC_DAIFMT_CLOCK_MASK);
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return -EINVAL;
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}
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snd_soc_component_update_bits(component, AB8500_DIGIFCONF1, mask, val);
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return 0;
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}
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static int ab8500_codec_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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{
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unsigned int mask;
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unsigned int val;
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struct snd_soc_component *component = dai->component;
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int status;
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unsigned int conf1_mask, conf1_val = 0;
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unsigned int conf2_mask, conf2_val = 0;
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unsigned int conf3_mask, conf3_val = 0;
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bool provider = false;
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int ret;
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dev_dbg(component->dev, "%s: Enter (fmt = 0x%x)\n", __func__, fmt);
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mask = BIT(AB8500_DIGIFCONF3_IF1DATOIF0AD) |
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conf3_mask = BIT(AB8500_DIGIFCONF3_IF1DATOIF0AD) |
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BIT(AB8500_DIGIFCONF3_IF1CLKTOIF0CLK) |
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BIT(AB8500_DIGIFCONF3_IF0BFIFOEN) |
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BIT(AB8500_DIGIFCONF3_IF0MASTER);
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val = 0;
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switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
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case SND_SOC_DAIFMT_CBP_CFP:
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dev_dbg(dai->component->dev,
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dev_dbg(component->dev,
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"%s: IF0 Master-mode: AB8500 provider.\n", __func__);
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val |= BIT(AB8500_DIGIFCONF3_IF0MASTER);
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conf3_val |= BIT(AB8500_DIGIFCONF3_IF0MASTER);
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provider = true;
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break;
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case SND_SOC_DAIFMT_CBC_CFC:
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dev_dbg(dai->component->dev,
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dev_dbg(component->dev,
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"%s: IF0 Master-mode: AB8500 consumer.\n", __func__);
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break;
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case SND_SOC_DAIFMT_CBC_CFP:
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case SND_SOC_DAIFMT_CBP_CFC:
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dev_err(dai->component->dev,
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dev_err(component->dev,
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"%s: ERROR: The device is either a provider or a consumer.\n",
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__func__);
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fallthrough;
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default:
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dev_err(dai->component->dev,
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"%s: ERROR: Unsupporter clocking mask 0x%x\n",
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dev_err(component->dev,
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"%s: ERROR: Unsupported clocking mask 0x%x\n",
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__func__, fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK);
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return -EINVAL;
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}
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snd_soc_component_update_bits(component, AB8500_DIGIFCONF3, mask, val);
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/* Set clock gating */
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status = ab8500_codec_set_dai_clock_gate(component, fmt);
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if (status) {
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dev_err(dai->component->dev,
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"%s: ERROR: Failed to set clock gate (%d).\n",
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__func__, status);
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return status;
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conf1_mask = BIT(AB8500_DIGIFCONF1_ENMASTGEN) |
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BIT(AB8500_DIGIFCONF1_ENFSBITCLK0);
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switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
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case SND_SOC_DAIFMT_CONT:
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if (provider)
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conf1_val = conf1_mask;
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break;
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case SND_SOC_DAIFMT_GATED:
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if (provider)
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conf1_val = BIT(AB8500_DIGIFCONF1_ENMASTGEN);
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break;
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default:
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dev_err(component->dev, "%s: Unsupported clock mask 0x%x\n",
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__func__, fmt & SND_SOC_DAIFMT_CLOCK_MASK);
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return -EINVAL;
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}
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/* Setting data transfer format */
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mask = BIT(AB8500_DIGIFCONF2_IF0FORMAT0) |
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BIT(AB8500_DIGIFCONF2_IF0FORMAT1) |
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BIT(AB8500_DIGIFCONF2_FSYNC0P) |
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BIT(AB8500_DIGIFCONF2_BITCLK0P);
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val = 0;
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conf2_mask = BIT(AB8500_DIGIFCONF2_IF0FORMAT0) |
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BIT(AB8500_DIGIFCONF2_IF0FORMAT1) |
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BIT(AB8500_DIGIFCONF2_IF0DEL) |
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BIT(AB8500_DIGIFCONF2_FSYNC0P) |
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BIT(AB8500_DIGIFCONF2_BITCLK0P);
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S: /* I2S mode */
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dev_dbg(dai->component->dev, "%s: IF0 Protocol: I2S\n", __func__);
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val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT1);
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ab8500_audio_set_bit_delay(dai, 0);
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dev_dbg(component->dev, "%s: IF0 Protocol: I2S\n", __func__);
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conf2_val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT1) |
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BIT(AB8500_DIGIFCONF2_IF0DEL);
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break;
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case SND_SOC_DAIFMT_DSP_A: /* L data MSB after FRM LRC */
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dev_dbg(dai->component->dev,
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dev_dbg(component->dev,
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"%s: IF0 Protocol: DSP A (TDM)\n", __func__);
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val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0);
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ab8500_audio_set_bit_delay(dai, 1);
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conf2_val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0) |
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BIT(AB8500_DIGIFCONF2_IF0DEL);
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break;
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case SND_SOC_DAIFMT_DSP_B: /* L data MSB during FRM LRC */
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dev_dbg(dai->component->dev,
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dev_dbg(component->dev,
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"%s: IF0 Protocol: DSP B (TDM)\n", __func__);
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val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0);
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ab8500_audio_set_bit_delay(dai, 0);
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conf2_val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0);
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break;
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default:
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dev_err(dai->component->dev,
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dev_err(component->dev,
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"%s: ERROR: Unsupported format (0x%x)!\n",
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__func__, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
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return -EINVAL;
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@ -1887,39 +1829,50 @@ static int ab8500_codec_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF: /* normal bit clock + frame */
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dev_dbg(dai->component->dev,
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dev_dbg(component->dev,
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"%s: IF0: Normal bit clock, normal frame\n",
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__func__);
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break;
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case SND_SOC_DAIFMT_NB_IF: /* normal BCLK + inv FRM */
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dev_dbg(dai->component->dev,
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dev_dbg(component->dev,
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"%s: IF0: Normal bit clock, inverted frame\n",
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__func__);
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val |= BIT(AB8500_DIGIFCONF2_FSYNC0P);
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conf2_val |= BIT(AB8500_DIGIFCONF2_FSYNC0P);
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break;
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case SND_SOC_DAIFMT_IB_NF: /* invert BCLK + nor FRM */
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dev_dbg(dai->component->dev,
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dev_dbg(component->dev,
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"%s: IF0: Inverted bit clock, normal frame\n",
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__func__);
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val |= BIT(AB8500_DIGIFCONF2_BITCLK0P);
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conf2_val |= BIT(AB8500_DIGIFCONF2_BITCLK0P);
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break;
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case SND_SOC_DAIFMT_IB_IF: /* invert BCLK + FRM */
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dev_dbg(dai->component->dev,
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dev_dbg(component->dev,
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"%s: IF0: Inverted bit clock, inverted frame\n",
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__func__);
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val |= BIT(AB8500_DIGIFCONF2_FSYNC0P);
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val |= BIT(AB8500_DIGIFCONF2_BITCLK0P);
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conf2_val |= BIT(AB8500_DIGIFCONF2_FSYNC0P) |
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BIT(AB8500_DIGIFCONF2_BITCLK0P);
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break;
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default:
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dev_err(dai->component->dev,
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dev_err(component->dev,
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"%s: ERROR: Unsupported INV mask 0x%x\n",
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__func__, fmt & SND_SOC_DAIFMT_INV_MASK);
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return -EINVAL;
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}
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snd_soc_component_update_bits(component, AB8500_DIGIFCONF2, mask, val);
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ret = snd_soc_component_update_bits(component, AB8500_DIGIFCONF3,
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conf3_mask, conf3_val);
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if (ret < 0)
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return ret;
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return 0;
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ret = snd_soc_component_update_bits(component, AB8500_DIGIFCONF1,
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conf1_mask, conf1_val);
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if (ret < 0)
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return ret;
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ret = snd_soc_component_update_bits(component, AB8500_DIGIFCONF2,
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conf2_mask, conf2_val);
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return ret < 0 ? ret : 0;
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}
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static int ab8500_codec_set_dai_tdm_slot(struct snd_soc_dai *dai,
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