From 9223cb663e9f3f1031f5ef9c6e398447e40338f6 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 28 Sep 2021 16:58:52 +0100 Subject: [PATCH 01/12] arm64: dts: renesas: r9a07g044: Add SPI Multi I/O Bus controller node Add SPI Multi I/O Bus controller node to R9A07G044 (RZ/G2L) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20210928155852.32569-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 4d4a23367529..1f01737d2def 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -358,6 +358,23 @@ channel@7 { }; }; + sbc: spi@10060000 { + compatible = "renesas,r9a07g044-rpc-if", + "renesas,rzg2l-rpc-if"; + reg = <0 0x10060000 0 0x10000>, + <0 0x20000000 0 0x10000000>, + <0 0x10070000 0 0x10000>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G044_SPI_CLK2>, + <&cpg CPG_MOD R9A07G044_SPI_CLK>; + resets = <&cpg R9A07G044_SPI_RST>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a07g044-cpg"; reg = <0 0x11010000 0 0x10000>; From 5de968a25a30302c7714ae1c80b0eaff6834e2ed Mon Sep 17 00:00:00 2001 From: Duc Nguyen Date: Wed, 6 Oct 2021 10:58:35 +0200 Subject: [PATCH 02/12] arm64: dts: renesas: r8a779a0: Add RPC node Add device node for RPC on R8A779A0 SoC. Signed-off-by: Duc Nguyen [wsa: rebased] Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20211006085836.42155-4-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index f9a882b34f82..2506db9525f4 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -1105,6 +1105,23 @@ mmc0: mmc@ee140000 { status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a779a0-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = ; + clocks = <&cpg CPG_MOD 629>; + clock-names = "rpc"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 629>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + ipmmu_rt0: iommu@ee480000 { compatible = "renesas,ipmmu-r8a779a0"; reg = <0 0xee480000 0 0x20000>; From f28daeedd7f920e172d60a97341be42430175a42 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 6 Oct 2021 10:58:36 +0200 Subject: [PATCH 03/12] arm64: dts: renesas: falcon-cpu: Add SPI flash via RPC Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20211006085836.42155-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi index d66e508a2334..cd2f0d60f21a 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi @@ -203,6 +203,11 @@ mmc_pins: mmc { power-source = <1800>; }; + qspi0_pins: qspi0 { + groups = "qspi0_ctrl", "qspi0_data4"; + function = "qspi0"; + }; + scif0_pins: scif0 { groups = "scif0_data", "scif0_ctrl"; function = "scif0"; @@ -214,6 +219,34 @@ scif_clk_pins: scif_clk { }; }; +&rpc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + flash@0 { + compatible = "spansion,s25fs512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + reg = <0x0 0xcc0000>; + read-only; + }; + user@cc0000 { + reg = <0xcc0000 0x3340000>; + }; + }; + }; +}; + &rwdt { timeout-sec = <60>; status = "okay"; From a83ad872f4ba6b9fbf81b9f70d6ff6d61d74bf7e Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 7 Oct 2021 16:54:49 +0100 Subject: [PATCH 04/12] arm64: dts: renesas: r9a07g044: Add SDHI nodes Add SDHI{0, 1} nodes to RZ/G2L SoC DTSI. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20211007155451.10654-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 1f01737d2def..0b0372a02515 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -456,6 +456,38 @@ gic: interrupt-controller@11900000 { interrupts = ; }; + sdhi0: mmc@11c00000 { + compatible = "renesas,sdhi-r9a07g044", + "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x11c00000 0 0x10000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>, + <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>, + <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>, + <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>; + clock-names = "imclk", "imclk2", "clk_hs", "aclk"; + resets = <&cpg R9A07G044_SDHI0_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + sdhi1: mmc@11c10000 { + compatible = "renesas,sdhi-r9a07g044", + "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x11c10000 0 0x10000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>, + <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>, + <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>, + <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>; + clock-names = "imclk", "imclk2", "clk_hs", "aclk"; + resets = <&cpg R9A07G044_SDHI1_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + phyrst: usbphy-ctrl@11c40000 { compatible = "renesas,r9a07g044-usbphy-ctrl", "renesas,rzg2l-usbphy-ctrl"; From a60a311cb8d0cddaaeb1eee22bfd76138e6b5ad6 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sun, 10 Oct 2021 15:25:19 +0100 Subject: [PATCH 05/12] arm64: dts: renesas: rzg2l-smarc-som: Enable eMMC on SMARC platform RZ/G2L SoM has both 64 GB eMMC and microSD connected to SDHI0. Both these interfaces are mutually exclusive and the SD0 device selection is based on the XOR between GPIO_SD0_DEV_SEL and SW1[2] switch position. This patch sets GPIO_SD0_DEV_SEL to high in DT. Use the below switch setting logic for device selection between eMMC and microSD slot connected to SDHI0. Set SW1[2] to position 2/OFF for selecting eMMC Set SW1[2] to position 3/ON for selecting microSD This patch enables eMMC on RZ/G2L SMARC platform by default. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20211010142520.21976-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/rzg2l-smarc-som.dtsi | 143 ++++++++++++++++++ 1 file changed, 143 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi index da1ee2206e1a..fbf51043d6cc 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi @@ -5,14 +5,55 @@ * Copyright (C) 2021 Renesas Electronics Corp. */ +#include #include +/* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */ +#define EMMC 1 + +/* + * To enable uSD card on CN3, + * SW1[2] should be at position 3/ON. + * Disable eMMC by setting "#define EMMC 0" above. + */ +#define SDHI (!EMMC) + / { memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x78000000>; }; + + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <3300000 1>, <1800000 0>; + regulator-boot-on; + gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; }; &adc { @@ -32,4 +73,106 @@ &pinctrl { adc_pins: adc { pinmux = ; /* ADC_TRG */ }; + + gpio-sd0-pwr-en-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "gpio_sd0_pwr_en"; + }; + + /* + * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2] + * The below switch logic can be used to select the device between + * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT. + * SW1[2] should be at position 2/OFF to enable 64 GB eMMC + * SW1[2] should be at position 3/ON to enable uSD card CN3 + */ + sd0-dev-sel-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "sd0_dev_sel"; + }; + + sdhi0_emmc_pins: sd0emmc { + sd0_emmc_data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7"; + power-source = <1800>; + }; + + sd0_emmc_ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <1800>; + }; + + sd0_emmc_rst { + pins = "SD0_RST#"; + power-source = <1800>; + }; + }; + + sdhi0_pins: sd0 { + sd0_data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; + power-source = <3300>; + }; + + sd0_ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <3300>; + }; + + sd0_mux { + pinmux = ; /* SD0_CD */ + }; + }; + + sdhi0_pins_uhs: sd0_uhs { + sd0_data_uhs { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; + power-source = <1800>; + }; + + sd0_ctrl_uhs { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <1800>; + }; + + sd0_mux_uhs { + pinmux = ; /* SD0_CD */ + }; + }; }; + +#if SDHI +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vccq_sdhi0>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; +#endif + +#if EMMC +&sdhi0 { + pinctrl-0 = <&sdhi0_emmc_pins>; + pinctrl-1 = <&sdhi0_emmc_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + fixed-emmc-driver-type = <1>; + status = "okay"; +}; +#endif From 34cdc0edfe8f6d660e3c4c47d10f5506d08f09e1 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sun, 10 Oct 2021 15:25:20 +0100 Subject: [PATCH 06/12] arm64: dts: renesas: rzg2l-smarc: Enable microSD on SMARC platform This patch enables microSD card slot connected to SDHI1 on RZ/G2L SMARC platform. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20211010142520.21976-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 62 ++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index a02784fab46a..d8b3d32dc6f5 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -70,6 +70,16 @@ usb0_vbus_otg: regulator-usb0-vbus-otg { regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + vccq_sdhi1: regulator-vccq-sdhi1 { + compatible = "regulator-gpio"; + regulator-name = "SDHI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; }; &audio_clk1{ @@ -199,6 +209,45 @@ scif0_pins: scif0 { ; /* RxD */ }; + sd1-pwr-en-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "sd1_pwr_en"; + }; + + sdhi1_pins: sd1 { + sd1_data { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <3300>; + }; + + sd1_ctrl { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <3300>; + }; + + sd1_mux { + pinmux = ; /* SD1_CD */ + }; + }; + + sdhi1_pins_uhs: sd1_uhs { + sd1_data_uhs { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <1800>; + }; + + sd1_ctrl_uhs { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <1800>; + }; + + sd1_mux_uhs { + pinmux = ; /* SD1_CD */ + }; + }; + sound_clk_pins: sound_clk { pins = "AUDIO_CLK1", "AUDIO_CLK2"; input-enable; @@ -229,6 +278,19 @@ &scif0 { status = "okay"; }; +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vccq_sdhi1>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + &ssi0 { pinctrl-0 = <&ssi0_pins>; pinctrl-names = "default"; From 5fea5b5571346981f060fd3b02658398048c3e91 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Tue, 12 Oct 2021 12:00:38 +0200 Subject: [PATCH 07/12] arm64: dts: renesas: r8a779a0: Add and connect all CSI-2, ISP and VIN nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The V3U have 32 VIN, 4 CSI-2 and 4 ISP nodes that interact with each other for video capture. Add all nodes and record how they are interconnected. Signed-off-by: Niklas Söderlund Link: https://lore.kernel.org/r/20211012100038.375289-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 1332 +++++++++++++++++++++ 1 file changed, 1332 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 2506db9525f4..43bf2cbfbd8f 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -1034,6 +1034,902 @@ msiof5: spi@e6c28000 { status = "disabled"; }; + vin00: video@e6ef0000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 730>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 730>; + renesas,id = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin00isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin00>; + }; + }; + }; + }; + + vin01: video@e6ef1000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 731>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 731>; + renesas,id = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin01isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin01>; + }; + }; + }; + }; + + vin02: video@e6ef2000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 800>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 800>; + renesas,id = <2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin02isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin02>; + }; + }; + }; + }; + + vin03: video@e6ef3000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 801>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 801>; + renesas,id = <3>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin03isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin03>; + }; + }; + }; + }; + + vin04: video@e6ef4000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6ef4000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 802>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 802>; + renesas,id = <4>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin04isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin04>; + }; + }; + }; + }; + + vin05: video@e6ef5000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6ef5000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 803>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 803>; + renesas,id = <5>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin05isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin05>; + }; + }; + }; + }; + + vin06: video@e6ef6000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6ef6000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 804>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 804>; + renesas,id = <6>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin06isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin06>; + }; + }; + }; + }; + + vin07: video@e6ef7000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6ef7000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 805>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 805>; + renesas,id = <7>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin07isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin07>; + }; + }; + }; + }; + + vin08: video@e6ef8000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6ef8000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 806>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 806>; + renesas,id = <8>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin08isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin08>; + }; + }; + }; + }; + + vin09: video@e6ef9000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6ef9000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 807>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 807>; + renesas,id = <9>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin09isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin09>; + }; + }; + }; + }; + + vin10: video@e6efa000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6efa000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 808>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 808>; + renesas,id = <10>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin10isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin10>; + }; + }; + }; + }; + + vin11: video@e6efb000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6efb000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 809>; + renesas,id = <11>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin11isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin11>; + }; + }; + }; + }; + + vin12: video@e6efc000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6efc000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 810>; + renesas,id = <12>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin12isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin12>; + }; + }; + }; + }; + + vin13: video@e6efd000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6efd000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 811>; + renesas,id = <13>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin13isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin13>; + }; + }; + }; + }; + + vin14: video@e6efe000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6efe000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 812>; + renesas,id = <14>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin14isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin14>; + }; + }; + }; + }; + + vin15: video@e6eff000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6eff000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 813>; + renesas,id = <15>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin15isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin15>; + }; + }; + }; + }; + + vin16: video@e6ed0000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6ed0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 814>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 814>; + renesas,id = <16>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin16isp2: endpoint@2 { + reg = <2>; + remote-endpoint = <&isp2vin16>; + }; + }; + }; + }; + + vin17: video@e6ed1000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6ed1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 815>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 815>; + renesas,id = <17>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin17isp2: endpoint@2 { + reg = <2>; + remote-endpoint = <&isp2vin17>; + }; + }; + }; + }; + + vin18: video@e6ed2000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6ed2000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 816>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 816>; + renesas,id = <18>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin18isp2: endpoint@2 { + reg = <2>; + remote-endpoint = <&isp2vin18>; + }; + }; + }; + }; + + vin19: video@e6ed3000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6ed3000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 817>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 817>; + renesas,id = <19>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin19isp2: endpoint@2 { + reg = <2>; + remote-endpoint = <&isp2vin19>; + }; + }; + }; + }; + + vin20: video@e6ed4000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6ed4000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 818>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 818>; + renesas,id = <20>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin20isp2: endpoint@2 { + reg = <2>; + remote-endpoint = <&isp2vin20>; + }; + }; + }; + }; + + vin21: video@e6ed5000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6ed5000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 819>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 819>; + renesas,id = <21>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin21isp2: endpoint@2 { + reg = <2>; + remote-endpoint = <&isp2vin21>; + }; + }; + }; + }; + + vin22: video@e6ed6000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6ed6000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 820>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 820>; + renesas,id = <22>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin22isp2: endpoint@2 { + reg = <2>; + remote-endpoint = <&isp2vin22>; + }; + }; + }; + }; + + vin23: video@e6ed7000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6ed7000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 821>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 821>; + renesas,id = <23>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin23isp2: endpoint@2 { + reg = <2>; + remote-endpoint = <&isp2vin23>; + }; + }; + }; + }; + + vin24: video@e6ed8000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6ed8000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 822>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 822>; + renesas,id = <24>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin24isp3: endpoint@3 { + reg = <3>; + remote-endpoint = <&isp3vin24>; + }; + }; + }; + }; + + vin25: video@e6ed9000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6ed9000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 823>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 823>; + renesas,id = <25>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin25isp3: endpoint@3 { + reg = <3>; + remote-endpoint = <&isp3vin25>; + }; + }; + }; + }; + + vin26: video@e6eda000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6eda000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 824>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 824>; + renesas,id = <26>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin26isp3: endpoint@3 { + reg = <3>; + remote-endpoint = <&isp3vin26>; + }; + }; + }; + }; + + vin27: video@e6edb000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6edb000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 825>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 825>; + renesas,id = <27>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin27isp3: endpoint@3 { + reg = <3>; + remote-endpoint = <&isp3vin27>; + }; + }; + }; + }; + + vin28: video@e6edc000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6edc000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 826>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 826>; + renesas,id = <28>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin28isp3: endpoint@3 { + reg = <3>; + remote-endpoint = <&isp3vin28>; + }; + }; + }; + }; + + vin29: video@e6edd000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6edd000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 827>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 827>; + renesas,id = <29>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin29isp3: endpoint@3 { + reg = <3>; + remote-endpoint = <&isp3vin29>; + }; + }; + }; + }; + + vin30: video@e6ede000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6ede000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 828>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 828>; + renesas,id = <30>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin30isp3: endpoint@3 { + reg = <3>; + remote-endpoint = <&isp3vin30>; + }; + }; + }; + }; + + vin31: video@e6edf000 { + compatible = "renesas,vin-r8a779a0"; + reg = <0 0xe6edf000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 829>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 829>; + renesas,id = <31>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin31isp3: endpoint@3 { + reg = <3>; + remote-endpoint = <&isp3vin31>; + }; + }; + }; + }; + dmac1: dma-controller@e7350000 { compatible = "renesas,dmac-r8a779a0"; reg = <0 0xe7350000 0 0x1000>, @@ -1268,6 +2164,442 @@ vspd1: vsp@fea28000 { renesas,fcp = <&fcpvd1>; }; + csi40: csi2@feaa0000 { + compatible = "renesas,r8a779a0-csi2"; + reg = <0 0xfeaa0000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 331>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + csi40isp0: endpoint { + remote-endpoint = <&isp0csi40>; + }; + }; + }; + }; + + csi41: csi2@feab0000 { + compatible = "renesas,r8a779a0-csi2"; + reg = <0 0xfeab0000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 400>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 400>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + csi41isp1: endpoint { + remote-endpoint = <&isp1csi41>; + }; + }; + }; + }; + + csi42: csi2@fed60000 { + compatible = "renesas,r8a779a0-csi2"; + reg = <0 0xfed60000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 401>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 401>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + csi42isp2: endpoint { + remote-endpoint = <&isp2csi42>; + }; + }; + }; + }; + + csi43: csi2@fed70000 { + compatible = "renesas,r8a779a0-csi2"; + reg = <0 0xfed70000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + csi43isp3: endpoint { + remote-endpoint = <&isp3csi43>; + }; + }; + }; + }; + + isp0: isp@fed00000 { + compatible = "renesas,r8a779a0-isp"; + reg = <0 0xfed00000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 612>; + power-domains = <&sysc R8A779A0_PD_A3ISP01>; + resets = <&cpg 612>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + + isp0csi40: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi40isp0>; + }; + }; + + port@1 { + reg = <1>; + isp0vin00: endpoint { + remote-endpoint = <&vin00isp0>; + }; + }; + + port@2 { + reg = <2>; + isp0vin01: endpoint { + remote-endpoint = <&vin01isp0>; + }; + }; + + port@3 { + reg = <3>; + isp0vin02: endpoint { + remote-endpoint = <&vin02isp0>; + }; + }; + + port@4 { + reg = <4>; + isp0vin03: endpoint { + remote-endpoint = <&vin03isp0>; + }; + }; + + port@5 { + reg = <5>; + isp0vin04: endpoint { + remote-endpoint = <&vin04isp0>; + }; + }; + + port@6 { + reg = <6>; + isp0vin05: endpoint { + remote-endpoint = <&vin05isp0>; + }; + }; + + port@7 { + reg = <7>; + isp0vin06: endpoint { + remote-endpoint = <&vin06isp0>; + }; + }; + + port@8 { + reg = <8>; + isp0vin07: endpoint { + remote-endpoint = <&vin07isp0>; + }; + }; + }; + }; + + isp1: isp@fed20000 { + compatible = "renesas,r8a779a0-isp"; + reg = <0 0xfed20000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 613>; + power-domains = <&sysc R8A779A0_PD_A3ISP01>; + resets = <&cpg 613>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + + isp1csi41: endpoint@1 { + reg = <1>; + remote-endpoint = <&csi41isp1>; + }; + }; + + port@1 { + reg = <1>; + isp1vin08: endpoint { + remote-endpoint = <&vin08isp1>; + }; + }; + + port@2 { + reg = <2>; + isp1vin09: endpoint { + remote-endpoint = <&vin09isp1>; + }; + }; + + port@3 { + reg = <3>; + isp1vin10: endpoint { + remote-endpoint = <&vin10isp1>; + }; + }; + + port@4 { + reg = <4>; + isp1vin11: endpoint { + remote-endpoint = <&vin11isp1>; + }; + }; + + port@5 { + reg = <5>; + isp1vin12: endpoint { + remote-endpoint = <&vin12isp1>; + }; + }; + + port@6 { + reg = <6>; + isp1vin13: endpoint { + remote-endpoint = <&vin13isp1>; + }; + }; + + port@7 { + reg = <7>; + isp1vin14: endpoint { + remote-endpoint = <&vin14isp1>; + }; + }; + + port@8 { + reg = <8>; + isp1vin15: endpoint { + remote-endpoint = <&vin15isp1>; + }; + }; + }; + }; + + isp2: isp@fed30000 { + compatible = "renesas,r8a779a0-isp"; + reg = <0 0xfed30000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 614>; + power-domains = <&sysc R8A779A0_PD_A3ISP23>; + resets = <&cpg 614>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + + isp2csi42: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi42isp2>; + }; + }; + + port@1 { + reg = <1>; + isp2vin16: endpoint { + remote-endpoint = <&vin16isp2>; + }; + }; + + port@2 { + reg = <2>; + isp2vin17: endpoint { + remote-endpoint = <&vin17isp2>; + }; + }; + + port@3 { + reg = <3>; + isp2vin18: endpoint { + remote-endpoint = <&vin18isp2>; + }; + }; + + port@4 { + reg = <4>; + isp2vin19: endpoint { + remote-endpoint = <&vin19isp2>; + }; + }; + + port@5 { + reg = <5>; + isp2vin20: endpoint { + remote-endpoint = <&vin20isp2>; + }; + }; + + port@6 { + reg = <6>; + isp2vin21: endpoint { + remote-endpoint = <&vin21isp2>; + }; + }; + + port@7 { + reg = <7>; + isp2vin22: endpoint { + remote-endpoint = <&vin22isp2>; + }; + }; + + port@8 { + reg = <8>; + isp2vin23: endpoint { + remote-endpoint = <&vin23isp2>; + }; + }; + }; + }; + + isp3: isp@fed40000 { + compatible = "renesas,r8a779a0-isp"; + reg = <0 0xfed40000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 615>; + power-domains = <&sysc R8A779A0_PD_A3ISP23>; + resets = <&cpg 615>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + + isp3csi43: endpoint@1 { + reg = <1>; + remote-endpoint = <&csi43isp3>; + }; + }; + + port@1 { + reg = <1>; + isp3vin24: endpoint { + remote-endpoint = <&vin24isp3>; + }; + }; + + port@2 { + reg = <2>; + isp3vin25: endpoint { + remote-endpoint = <&vin25isp3>; + }; + }; + + port@3 { + reg = <3>; + isp3vin26: endpoint { + remote-endpoint = <&vin26isp3>; + }; + }; + + port@4 { + reg = <4>; + isp3vin27: endpoint { + remote-endpoint = <&vin27isp3>; + }; + }; + + port@5 { + reg = <5>; + isp3vin28: endpoint { + remote-endpoint = <&vin28isp3>; + }; + }; + + port@6 { + reg = <6>; + isp3vin29: endpoint { + remote-endpoint = <&vin29isp3>; + }; + }; + + port@7 { + reg = <7>; + isp3vin30: endpoint { + remote-endpoint = <&vin30isp3>; + }; + }; + + port@8 { + reg = <8>; + isp3vin31: endpoint { + remote-endpoint = <&vin31isp3>; + }; + }; + }; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; From c534e655d5b385ace4bd6394865508edd546d4c9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Tue, 12 Oct 2021 20:34:31 +0200 Subject: [PATCH 08/12] arm64: dts: renesas: Add ports node to all adv7482 nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The different port@ entries of the adv7482 nodes shall be encapsulated in a ports node, add one. This change does not change how the driver parses the DT and no driver change is needed. The change however makes it possible to validate the source files with a correct json-schema. Signed-off-by: Niklas Söderlund Link: https://lore.kernel.org/r/20211012183431.718691-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/ebisu.dtsi | 40 +++++++------- .../boot/dts/renesas/salvator-common.dtsi | 54 ++++++++++--------- 2 files changed, 49 insertions(+), 45 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/ebisu.dtsi b/arch/arm64/boot/dts/renesas/ebisu.dtsi index 0fdfc67cb965..67231c8576c5 100644 --- a/arch/arm64/boot/dts/renesas/ebisu.dtsi +++ b/arch/arm64/boot/dts/renesas/ebisu.dtsi @@ -423,37 +423,39 @@ video-receiver@70 { compatible = "adi,adv7482"; reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&gpio0>; interrupt-names = "intrq1", "intrq2"; interrupts = <7 IRQ_TYPE_LEVEL_LOW>, <17 IRQ_TYPE_LEVEL_LOW>; - port@7 { - reg = <7>; + ports { + #address-cells = <1>; + #size-cells = <0>; - adv7482_ain7: endpoint { - remote-endpoint = <&cvbs_con>; + port@7 { + reg = <7>; + + adv7482_ain7: endpoint { + remote-endpoint = <&cvbs_con>; + }; }; - }; - port@8 { - reg = <8>; + port@8 { + reg = <8>; - adv7482_hdmi: endpoint { - remote-endpoint = <&hdmi_in_con>; + adv7482_hdmi: endpoint { + remote-endpoint = <&hdmi_in_con>; + }; }; - }; - port@a { - reg = <10>; + port@a { + reg = <10>; - adv7482_txa: endpoint { - clock-lanes = <0>; - data-lanes = <1 2>; - remote-endpoint = <&csi40_in>; + adv7482_txa: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&csi40_in>; + }; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index df2d69075ffd..bf37777dca31 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -526,47 +526,49 @@ video-receiver@70 { reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater", "infoframe", "cbus", "cec", "sdp", "txa", "txb" ; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&gpio6>; interrupt-names = "intrq1", "intrq2"; interrupts = <30 IRQ_TYPE_LEVEL_LOW>, <31 IRQ_TYPE_LEVEL_LOW>; - port@7 { - reg = <7>; + ports { + #address-cells = <1>; + #size-cells = <0>; - adv7482_ain7: endpoint { - remote-endpoint = <&cvbs_con>; + port@7 { + reg = <7>; + + adv7482_ain7: endpoint { + remote-endpoint = <&cvbs_con>; + }; }; - }; - port@8 { - reg = <8>; + port@8 { + reg = <8>; - adv7482_hdmi: endpoint { - remote-endpoint = <&hdmi_in_con>; + adv7482_hdmi: endpoint { + remote-endpoint = <&hdmi_in_con>; + }; }; - }; - port@a { - reg = <10>; + port@a { + reg = <10>; - adv7482_txa: endpoint { - clock-lanes = <0>; - data-lanes = <1 2 3 4>; - remote-endpoint = <&csi40_in>; + adv7482_txa: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi40_in>; + }; }; - }; - port@b { - reg = <11>; + port@b { + reg = <11>; - adv7482_txb: endpoint { - clock-lanes = <0>; - data-lanes = <1>; - remote-endpoint = <&csi20_in>; + adv7482_txb: endpoint { + clock-lanes = <0>; + data-lanes = <1>; + remote-endpoint = <&csi20_in>; + }; }; }; }; From 38ad23e15a02f4001cd0048617f85522c37e0e8a Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 13 Oct 2021 08:56:46 +0100 Subject: [PATCH 09/12] arm64: dts: renesas: r9a07g044: Add GbEthernet nodes Add Gigabit Ethernet{0,1} nodes to SoC DTSI. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20211013075647.32231-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 0b0372a02515..485ef5f0fea1 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -488,6 +488,46 @@ sdhi1: mmc@11c10000 { status = "disabled"; }; + eth0: ethernet@11c20000 { + compatible = "renesas,r9a07g044-gbeth", + "renesas,rzg2l-gbeth"; + reg = <0 0x11c20000 0 0x10000>; + interrupts = , + , + ; + interrupt-names = "mux", "fil", "arp_ns"; + phy-mode = "rgmii"; + clocks = <&cpg CPG_MOD R9A07G044_ETH0_CLK_AXI>, + <&cpg CPG_MOD R9A07G044_ETH0_CLK_CHI>, + <&cpg CPG_CORE R9A07G044_CLK_HP>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A07G044_ETH0_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + eth1: ethernet@11c30000 { + compatible = "renesas,r9a07g044-gbeth", + "renesas,rzg2l-gbeth"; + reg = <0 0x11c30000 0 0x10000>; + interrupts = , + , + ; + interrupt-names = "mux", "fil", "arp_ns"; + phy-mode = "rgmii"; + clocks = <&cpg CPG_MOD R9A07G044_ETH1_CLK_AXI>, + <&cpg CPG_MOD R9A07G044_ETH1_CLK_CHI>, + <&cpg CPG_CORE R9A07G044_CLK_HP>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A07G044_ETH1_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + phyrst: usbphy-ctrl@11c40000 { compatible = "renesas,r9a07g044-usbphy-ctrl", "renesas,rzg2l-usbphy-ctrl"; From 361b0dcbd7f9b01d92fdcb032ed4e020941183eb Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 13 Oct 2021 08:56:47 +0100 Subject: [PATCH 10/12] arm64: dts: renesas: rzg2l-smarc-som: Enable Ethernet Enable Ethernet{0,1} interfaces on RZ/G2L SMARC EVK. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20211013075647.32231-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/rzg2l-smarc-som.dtsi | 97 +++++++++++++++++++ arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 1 - 2 files changed, 97 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi index fbf51043d6cc..7e84a29dddfa 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi @@ -19,6 +19,15 @@ #define SDHI (!EMMC) / { + aliases { + ethernet0 = ð0; + ethernet1 = ð1; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + }; + memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ @@ -65,6 +74,58 @@ &adc { /delete-node/ channel@7; }; +ð0 { + pinctrl-0 = <ð0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy0: ethernet-phy@7 { + compatible = "ethernet-phy-id0022.1640", + "ethernet-phy-ieee802.3-c22"; + reg = <7>; + rxc-skew-psec = <2400>; + txc-skew-psec = <2400>; + rxdv-skew-psec = <0>; + txdv-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; + +ð1 { + pinctrl-0 = <ð1_pins>; + pinctrl-names = "default"; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy1: ethernet-phy@7 { + compatible = "ethernet-phy-id0022.1640", + "ethernet-phy-ieee802.3-c22"; + reg = <7>; + rxc-skew-psec = <2400>; + txc-skew-psec = <2400>; + rxdv-skew-psec = <0>; + txdv-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; + &extal_clk { clock-frequency = <24000000>; }; @@ -74,6 +135,42 @@ adc_pins: adc { pinmux = ; /* ADC_TRG */ }; + eth0_pins: eth0 { + pinmux = , /* ET0_LINKSTA */ + , /* ET0_MDC */ + , /* ET0_MDIO */ + , /* ET0_TXC */ + , /* ET0_TX_CTL */ + , /* ET0_TXD0 */ + , /* ET0_TXD1 */ + , /* ET0_TXD2 */ + , /* ET0_TXD3 */ + , /* ET0_RXC */ + , /* ET0_RX_CTL */ + , /* ET0_RXD0 */ + , /* ET0_RXD1 */ + , /* ET0_RXD2 */ + ; /* ET0_RXD3 */ + }; + + eth1_pins: eth1 { + pinmux = , /* ET1_LINKSTA */ + , /* ET1_MDC */ + , /* ET1_MDIO */ + , /* ET1_TXC */ + , /* ET1_TX_CTL */ + , /* ET1_TXD0 */ + , /* ET1_TXD1 */ + , /* ET1_TXD2 */ + , /* ET1_TXD3 */ + , /* ET1_RXC */ + , /* ET1_RX_CTL */ + , /* ET1_RXD0 */ + , /* ET1_RXD1 */ + , /* ET1_RXD2 */ + ; /* ET1_RXD3 */ + }; + gpio-sd0-pwr-en-hog { gpio-hog; gpios = ; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index d8b3d32dc6f5..2863e487a640 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -30,7 +30,6 @@ aliases { }; chosen { - bootargs = "ignore_loglevel"; stdout-path = "serial0:115200n8"; }; From 12ee3118871f9ddc75e5551e85c5de7fd5c7f86a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 14 Oct 2021 10:36:07 +0200 Subject: [PATCH 11/12] arm64: dts: renesas: rcar-gen3e: Add Cortex-A57 2 GHz opps Add operating points for running the Cortex-A57 CPU cores on R-Car H3e-2G, M3e-2G, and M3Ne-2G at 2 GHz. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/08a0f27f50b8ad4a78c05186190bebcfb364fe8f.1634200489.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779m1.dtsi | 9 +++++++++ arch/arm64/boot/dts/renesas/r8a779m3.dtsi | 9 +++++++++ arch/arm64/boot/dts/renesas/r8a779m5.dtsi | 9 +++++++++ 3 files changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779m1.dtsi b/arch/arm64/boot/dts/renesas/r8a779m1.dtsi index 0e9b04469b83..b6e855f52adf 100644 --- a/arch/arm64/boot/dts/renesas/r8a779m1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779m1.dtsi @@ -10,3 +10,12 @@ / { compatible = "renesas,r8a779m1", "renesas,r8a7795"; }; + +&cluster0_opp { + opp-2000000000 { + opp-hz = /bits/ 64 <2000000000>; + opp-microvolt = <960000>; + clock-latency-ns = <300000>; + turbo-mode; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779m3.dtsi b/arch/arm64/boot/dts/renesas/r8a779m3.dtsi index 65bb6188ccf5..6cff38a6d20b 100644 --- a/arch/arm64/boot/dts/renesas/r8a779m3.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779m3.dtsi @@ -10,3 +10,12 @@ / { compatible = "renesas,r8a779m3", "renesas,r8a77961"; }; + +&cluster0_opp { + opp-2000000000 { + opp-hz = /bits/ 64 <2000000000>; + opp-microvolt = <960000>; + clock-latency-ns = <300000>; + turbo-mode; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779m5.dtsi b/arch/arm64/boot/dts/renesas/r8a779m5.dtsi index f0ef765f6cf8..8c9c0557fe77 100644 --- a/arch/arm64/boot/dts/renesas/r8a779m5.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779m5.dtsi @@ -10,3 +10,12 @@ / { compatible = "renesas,r8a779m5", "renesas,r8a77965"; }; + +&cluster0_opp { + opp-2000000000 { + opp-hz = /bits/ 64 <2000000000>; + opp-microvolt = <960000>; + clock-latency-ns = <300000>; + turbo-mode; + }; +}; From 6be85db40135fb55883f35476a1edd00eb7a9a6b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Thu, 14 Oct 2021 23:29:06 +0200 Subject: [PATCH 12/12] =?UTF-8?q?mailmap:=20Fix=20text=20encoding=20for=20?= =?UTF-8?q?Niklas=20S=C3=B6derlund?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are commits that mess up the encoding of 'ö' in Söderlund, add a correct entry to .mailmap. Signed-off-by: Niklas Söderlund Link: https://lore.kernel.org/r/20211014212906.2331293-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- .mailmap | 1 + 1 file changed, 1 insertion(+) diff --git a/.mailmap b/.mailmap index 6e849110cb4e..1c89a4486269 100644 --- a/.mailmap +++ b/.mailmap @@ -276,6 +276,7 @@ Nicolas Pitre Nicolas Pitre Nicolas Saenz Julienne Nicolas Saenz Julienne +Niklas Söderlund Oleksij Rempel Oleksij Rempel Oleksij Rempel