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arm64: dts: qcom: sm8250: switch PCIe QMP PHY to new style of bindings

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Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230820142035.89903-17-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Dmitry Baryshkov 2023-08-20 17:20:33 +03:00 committed by Bjorn Andersson
parent aeda057881
commit f96babe4b0
1 changed files with 45 additions and 67 deletions
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112
arch/arm64/boot/dts/qcom/sm8250.dtsi
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@ -2185,7 +2185,7 @@ pcie0: pci@1c00000 {
power-domains = <&gcc PCIE_0_GDSC>;
phys = <&pcie0_lane>;
phys = <&pcie0_phy>;
phy-names = "pciephy";
perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
@ -2200,15 +2200,23 @@ pcie0: pci@1c00000 {
pcie0_phy: phy@1c06000 {
compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
reg = <0 0x01c06000 0 0x1c0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
reg = <0 0x01c06000 0 0x1000>;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_WIFI_CLKREF_EN>,
<&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "refgen";
<&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
<&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "aux",
"cfg_ahb",
"ref",
"refgen",
"pipe";
clock-output-names = "pcie_0_pipe_clk";
#clock-cells = <0>;
#phy-cells = <0>;
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "phy";
@ -2217,20 +2225,6 @@ pcie0_phy: phy@1c06000 {
assigned-clock-rates = <100000000>;
status = "disabled";
pcie0_lane: phy@1c06200 {
reg = <0 0x01c06200 0 0x170>, /* tx */
<0 0x01c06400 0 0x200>, /* rx */
<0 0x01c06800 0 0x1f0>, /* pcs */
<0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "pipe0";
#phy-cells = <0>;
#clock-cells = <0>;
clock-output-names = "pcie_0_pipe_clk";
};
};
pcie1: pci@1c08000 {
@ -2292,7 +2286,7 @@ pcie1: pci@1c08000 {
power-domains = <&gcc PCIE_1_GDSC>;
phys = <&pcie1_lane>;
phys = <&pcie1_phy>;
phy-names = "pciephy";
perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
@ -2307,15 +2301,23 @@ pcie1: pci@1c08000 {
pcie1_phy: phy@1c0e000 {
compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
reg = <0 0x01c0e000 0 0x1c0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
reg = <0 0x01c0e000 0 0x1000>;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
<&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "refgen";
<&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
<&gcc GCC_PCIE_1_PIPE_CLK>;
clock-names = "aux",
"cfg_ahb",
"ref",
"refgen",
"pipe";
clock-output-names = "pcie_1_pipe_clk";
#clock-cells = <0>;
#phy-cells = <0>;
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
reset-names = "phy";
@ -2324,22 +2326,6 @@ pcie1_phy: phy@1c0e000 {
assigned-clock-rates = <100000000>;
status = "disabled";
pcie1_lane: phy@1c0e200 {
reg = <0 0x01c0e200 0 0x170>, /* tx0 */
<0 0x01c0e400 0 0x200>, /* rx0 */
<0 0x01c0ea00 0 0x1f0>, /* pcs */
<0 0x01c0e600 0 0x170>, /* tx1 */
<0 0x01c0e800 0 0x200>, /* rx1 */
<0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
clock-names = "pipe0";
#phy-cells = <0>;
#clock-cells = <0>;
clock-output-names = "pcie_1_pipe_clk";
};
};
pcie2: pci@1c10000 {
@ -2401,7 +2387,7 @@ pcie2: pci@1c10000 {
power-domains = <&gcc PCIE_2_GDSC>;
phys = <&pcie2_lane>;
phys = <&pcie2_phy>;
phy-names = "pciephy";
perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
@ -2416,15 +2402,23 @@ pcie2: pci@1c10000 {
pcie2_phy: phy@1c16000 {
compatible = "qcom,sm8250-qmp-modem-pcie-phy";
reg = <0 0x01c16000 0 0x1c0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
reg = <0 0x01c16000 0 0x1000>;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
<&gcc GCC_PCIE_MDM_CLKREF_EN>,
<&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "refgen";
<&gcc GCC_PCIE2_PHY_REFGEN_CLK>,
<&gcc GCC_PCIE_2_PIPE_CLK>;
clock-names = "aux",
"cfg_ahb",
"ref",
"refgen",
"pipe";
clock-output-names = "pcie_2_pipe_clk";
#clock-cells = <0>;
#phy-cells = <0>;
resets = <&gcc GCC_PCIE_2_PHY_BCR>;
reset-names = "phy";
@ -2433,22 +2427,6 @@ pcie2_phy: phy@1c16000 {
assigned-clock-rates = <100000000>;
status = "disabled";
pcie2_lane: phy@1c16200 {
reg = <0 0x01c16200 0 0x170>, /* tx0 */
<0 0x01c16400 0 0x200>, /* rx0 */
<0 0x01c16a00 0 0x1f0>, /* pcs */
<0 0x01c16600 0 0x170>, /* tx1 */
<0 0x01c16800 0 0x200>, /* rx1 */
<0 0x01c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
clock-names = "pipe0";
#phy-cells = <0>;
#clock-cells = <0>;
clock-output-names = "pcie_2_pipe_clk";
};
};
ufs_mem_hc: ufshc@1d84000 {