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net/mlx5: Add IFC bits for shared headroom pool PBMC support

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Add hardware interface definitions for shared headroom pool (SHP) in
port buffer management:

- shp_pbmc_pbsr_support: capability bit in PCAM enhanced features
  indicating device support for shared headroom pool in PBMC/PBSR.
- shared_headroom_pool: buffer entry in PBMC register (pbmc_reg_bits)
  for the shared headroom pool configuration, reusing the bufferx
  layout; reduce trailing reserved region accordingly.

Signed-off-by: Alexei Lazar <alazar@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/20260309093435.1850724-2-tariqt@nvidia.com
Signed-off-by: Leon Romanovsky <leon@kernel.org>
This commit is contained in:
Alexei Lazar 2026-03-09 11:34:27 +02:00 committed by Leon Romanovsky
parent 385a06f74f
commit f8e7616559
1 changed files with 5 additions and 2 deletions
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7
include/linux/mlx5/mlx5_ifc.h
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@ -10845,7 +10845,9 @@ struct mlx5_ifc_pcam_enhanced_features_bits {
u8 fec_200G_per_lane_in_pplm[0x1];
u8 reserved_at_1e[0x2a];
u8 fec_100G_per_lane_in_pplm[0x1];
u8 reserved_at_49[0xa];
u8 reserved_at_49[0x2];
u8 shp_pbmc_pbsr_support[0x1];
u8 reserved_at_4c[0x7];
u8 buffer_ownership[0x1];
u8 resereved_at_54[0x14];
u8 fec_50G_per_lane_in_pplm[0x1];
@ -12090,8 +12092,9 @@ struct mlx5_ifc_pbmc_reg_bits {
u8 port_buffer_size[0x10];
struct mlx5_ifc_bufferx_reg_bits buffer[10];
struct mlx5_ifc_bufferx_reg_bits shared_headroom_pool;
u8 reserved_at_2e0[0x80];
u8 reserved_at_320[0x40];
};
struct mlx5_ifc_sbpr_reg_bits {