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clk: renesas: rzg2l: Re-assert reset on deassert timeout

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Prevent issues during reset deassertion by re-asserting the reset if a
timeout occurs when trying to deassert. This ensures the reset line is in a
known state and improves reliability for hardware that may not immediately
clear the reset monitor bit.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Link: https://lore.kernel.org/20250903082757.115778-3-tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Tommaso Merciai 2025-09-03 10:27:51 +02:00 committed by Geert Uytterhoeven
parent 341b0f1b6c
commit f8c5f0dc77
1 changed files with 8 additions and 2 deletions
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10
drivers/clk/renesas/rzg2l-cpg.c
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@ -1667,8 +1667,14 @@ static int __rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
return 0;
}
return readl_poll_timeout_atomic(priv->base + reg, value,
assert == !!(value & mask), 10, 200);
ret = readl_poll_timeout_atomic(priv->base + reg, value,
assert == !!(value & mask), 10, 200);
if (ret && !assert) {
value = mask << 16;
writel(value, priv->base + CLK_RST_R(info->resets[id].off));
}
return ret;
}
static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev,