From f8c172660a2a08cfdd17b0394168e03f07feada2 Mon Sep 17 00:00:00 2001 From: Ankit Nautiyal Date: Mon, 2 Feb 2026 16:07:20 +0530 Subject: [PATCH] drm/i915/dp_mst: Move the check for dotclock at the end Refactor the mode_valid to have all joiner dependent stuff together and place the check for dotclock limit at the very end. This will help in the following refactor to iterate over the joiner candidates and find the best joiner candidate that satisfy all checks and limits. v2: Update status to MODE_CLOCK_HIGH if max_dotclock check fails. (Imre) v3: Drop redundant MODE_OK assignment and return. (Imre) Signed-off-by: Ankit Nautiyal Reviewed-by: Imre Deak Link: https://patch.msgid.link/20260202103731.357416-7-ankit.k.nautiyal@intel.com --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 24f8e60df9ac..ec6882af0631 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1470,20 +1470,19 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector, * corresponding link capabilities of the sink) in case the * stream is uncompressed for it by the last branch device. */ - num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector, - mode->hdisplay, target_clock); - max_dotclk *= num_joined_pipes; - ret = drm_modeset_lock(&mgr->base.lock, ctx); if (ret) return ret; - if (mode_rate > max_rate || mode->clock > max_dotclk || + if (mode_rate > max_rate || drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) { *status = MODE_CLOCK_HIGH; return 0; } + num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector, + mode->hdisplay, target_clock); + if (intel_dp_has_dsc(connector) && drm_dp_sink_supports_fec(connector->dp.fec_capability)) { /* * TBD pass the connector BPC, @@ -1513,6 +1512,15 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector, } *status = intel_mode_valid_max_plane_size(display, mode, num_joined_pipes); + + if (*status != MODE_OK) + return 0; + + max_dotclk *= num_joined_pipes; + + if (mode->clock > max_dotclk) + *status = MODE_CLOCK_HIGH; + return 0; }