From f8b9431ee38ed561650be7092ab93f564598daa9 Mon Sep 17 00:00:00 2001 From: Liang Chen Date: Thu, 6 Apr 2023 16:49:43 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3568: support adjust opp-table by otp Signed-off-by: Liang Chen Change-Id: I93bac848a43a06c90e436b4c2c36cc6ed1a8bc71 --- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 156 ++++++++++++++--------- 1 file changed, 95 insertions(+), 61 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 3ba069f4a991..c28278bc5642 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -125,12 +125,14 @@ cpu0_opp_table: cpu0-opp-table { opp-shared; mbist-vmin = <825000 900000 950000>; - nvmem-cells = <&cpu_leakage>, <&core_pvtm>, <&mbist_vmin>; - nvmem-cell-names = "leakage", "pvtm", "mbist-vmin"; + nvmem-cells = <&cpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&cpu_opp_info>; + nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info"; + rockchip,max-volt = <1150000>; rockchip,pvtm-voltage-sel = < 0 84000 0 - 84001 91000 1 - 91001 100000 2 + 84001 87000 1 + 87001 91000 2 + 91001 100000 3 >; rockchip,pvtm-freq = <408000>; rockchip,pvtm-volt = <900000>; @@ -145,7 +147,7 @@ cpu0_opp_table: cpu0-opp-table { rockchip,low-temp = <0>; rockchip,low-temp-adjust-volt = < /* MHz MHz uV */ - 0 1608 75000 + 0 1992 75000 >; opp-408000000 { @@ -170,38 +172,43 @@ opp-1104000000 { opp-microvolt-L0 = <900000 900000 1150000>; opp-microvolt-L1 = <850000 850000 1150000>; opp-microvolt-L2 = <850000 850000 1150000>; + opp-microvolt-L3 = <850000 850000 1150000>; clock-latency-ns = <40000>; }; opp-1416000000 { opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1000000 1000000 1150000>; - opp-microvolt-L0 = <1000000 1000000 1150000>; - opp-microvolt-L1 = <925000 925000 1150000>; - opp-microvolt-L2 = <925000 925000 1150000>; + opp-microvolt = <1025000 1025000 1150000>; + opp-microvolt-L0 = <1025000 1025000 1150000>; + opp-microvolt-L1 = <975000 975000 1150000>; + opp-microvolt-L2 = <950000 950000 1150000>; + opp-microvolt-L3 = <925000 925000 1150000>; clock-latency-ns = <40000>; }; opp-1608000000 { opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <1075000 1075000 1150000>; - opp-microvolt-L0 = <1075000 1075000 1150000>; - opp-microvolt-L1 = <1000000 1000000 1150000>; - opp-microvolt-L2 = <1000000 1000000 1150000>; + opp-microvolt = <1100000 1100000 1150000>; + opp-microvolt-L0 = <1100000 1100000 1150000>; + opp-microvolt-L1 = <1050000 1050000 1150000>; + opp-microvolt-L2 = <1025000 1025000 1150000>; + opp-microvolt-L3 = <1000000 1000000 1150000>; clock-latency-ns = <40000>; }; opp-1800000000 { opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1125000 1125000 1150000>; - opp-microvolt-L0 = <1125000 1125000 1150000>; - opp-microvolt-L1 = <1050000 1050000 1150000>; - opp-microvolt-L2 = <1050000 1050000 1150000>; + opp-microvolt = <1150000 1150000 1150000>; + opp-microvolt-L0 = <1150000 1150000 1150000>; + opp-microvolt-L1 = <1100000 1100000 1150000>; + opp-microvolt-L2 = <1075000 1075000 1150000>; + opp-microvolt-L3 = <1050000 1050000 1150000>; clock-latency-ns = <40000>; }; opp-1992000000 { opp-hz = /bits/ 64 <1992000000>; opp-microvolt = <1150000 1150000 1150000>; opp-microvolt-L0 = <1150000 1150000 1150000>; - opp-microvolt-L1 = <1100000 1100000 1150000>; - opp-microvolt-L2 = <1075000 1075000 1150000>; + opp-microvolt-L1 = <1150000 1150000 1150000>; + opp-microvolt-L2 = <1125000 1125000 1150000>; + opp-microvolt-L3 = <1100000 1100000 1150000>; clock-latency-ns = <40000>; }; }; @@ -292,7 +299,7 @@ scmi_clk: protocol@14 { reg = <0x14>; #clock-cells = <1>; - rockchip,clk-init = <1416000000>; + rockchip,clk-init = <1104000000>; }; }; @@ -1097,18 +1104,20 @@ npu_opp_table: npu-opp-table { compatible = "operating-points-v2"; mbist-vmin = <825000 900000 950000>; - nvmem-cells = <&npu_leakage>, <&core_pvtm>, <&mbist_vmin>; - nvmem-cell-names = "leakage", "pvtm", "mbist-vmin"; + nvmem-cells = <&npu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&npu_opp_info>; + nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info"; + rockchip,max-volt = <1000000>; rockchip,temp-hysteresis = <5000>; rockchip,low-temp = <0>; rockchip,low-temp-adjust-volt = < /* MHz MHz uV */ - 0 700 50000 + 0 1000 50000 >; rockchip,pvtm-voltage-sel = < 0 84000 0 - 84001 91000 1 - 91001 100000 2 + 84001 87000 1 + 87001 91000 2 + 91001 100000 3 >; rockchip,pvtm-ch = <0 5>; @@ -1126,38 +1135,39 @@ opp-400000000 { }; opp-600000000 { opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <850000 850000 1000000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; opp-microvolt = <875000 875000 1000000>; opp-microvolt-L0 = <875000 875000 1000000>; opp-microvolt-L1 = <850000 850000 1000000>; opp-microvolt-L2 = <850000 850000 1000000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <900000 900000 1000000>; - opp-microvolt-L0 = <900000 900000 1000000>; - opp-microvolt-L1 = <850000 850000 1000000>; - opp-microvolt-L2 = <850000 850000 1000000>; + opp-microvolt-L3 = <850000 850000 1000000>; }; opp-800000000 { opp-hz = /bits/ 64 <800000000>; opp-microvolt = <925000 925000 1000000>; opp-microvolt-L0 = <925000 925000 1000000>; - opp-microvolt-L1 = <875000 875000 1000000>; + opp-microvolt-L1 = <900000 900000 1000000>; opp-microvolt-L2 = <875000 875000 1000000>; + opp-microvolt-L3 = <875000 875000 1000000>; }; opp-900000000 { opp-hz = /bits/ 64 <900000000>; opp-microvolt = <975000 975000 1000000>; opp-microvolt-L0 = <975000 975000 1000000>; - opp-microvolt-L1 = <925000 925000 1000000>; - opp-microvolt-L2 = <900000 900000 1000000>; + opp-microvolt-L1 = <950000 950000 1000000>; + opp-microvolt-L2 = <925000 925000 1000000>; + opp-microvolt-L3 = <900000 900000 1000000>; }; opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <1000000 1000000 1000000>; opp-microvolt-L0 = <1000000 1000000 1000000>; - opp-microvolt-L1 = <950000 950000 1000000>; - opp-microvolt-L2 = <925000 925000 1000000>; + opp-microvolt-L1 = <975000 975000 1000000>; + opp-microvolt-L2 = <950000 950000 1000000>; + opp-microvolt-L3 = <925000 925000 1000000>; status = "disabled"; }; }; @@ -1250,47 +1260,58 @@ gpu_opp_table: opp-table2 { compatible = "operating-points-v2"; mbist-vmin = <825000 900000 950000>; - nvmem-cells = <&gpu_leakage>, <&core_pvtm>, <&mbist_vmin>; - nvmem-cell-names = "leakage", "pvtm", "mbist-vmin"; + nvmem-cells = <&gpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&gpu_opp_info>; + nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info"; + rockchip,max-volt = <1000000>; + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <0>; + rockchip,low-temp-adjust-volt = < + /* MHz MHz uV */ + 0 800 50000 + >; rockchip,pvtm-voltage-sel = < 0 84000 0 - 84001 91000 1 - 91001 100000 2 + 84001 87000 1 + 87001 91000 2 + 91001 100000 3 >; rockchip,pvtm-ch = <0 5>; opp-200000000 { opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <850000>; + opp-microvolt = <850000 850000 1000000>; }; opp-300000000 { opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <850000>; + opp-microvolt = <850000 850000 1000000>; }; opp-400000000 { opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <850000>; + opp-microvolt = <850000 850000 1000000>; }; opp-600000000 { opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <875000>; - opp-microvolt-L0 = <875000>; - opp-microvolt-L1 = <850000>; - opp-microvolt-L2 = <850000>; + opp-microvolt = <900000 900000 1000000>; + opp-microvolt-L0 = <900000 900000 1000000>; + opp-microvolt-L1 = <875000 875000 1000000>; + opp-microvolt-L2 = <850000 850000 1000000>; + opp-microvolt-L3 = <850000 850000 1000000>; }; opp-700000000 { opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <950000>; - opp-microvolt-L0 = <950000>; - opp-microvolt-L1 = <900000>; - opp-microvolt-L2 = <850000>; + opp-microvolt = <950000 950000 1000000>; + opp-microvolt-L0 = <950000 950000 1000000>; + opp-microvolt-L1 = <925000 925000 1000000>; + opp-microvolt-L2 = <900000 900000 1000000>; + opp-microvolt-L3 = <875000 875000 1000000>; }; opp-800000000 { opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1000000>; - opp-microvolt-L0 = <1000000>; - opp-microvolt-L1 = <950000>; - opp-microvolt-L2 = <900000>; + opp-microvolt = <1000000 1000000 1000000>; + opp-microvolt-L0 = <1000000 1000000 1000000>; + opp-microvolt-L1 = <975000 975000 1000000>; + opp-microvolt-L2 = <950000 950000 1000000>; + opp-microvolt-L3 = <925000 925000 1000000>; }; }; @@ -2303,8 +2324,9 @@ dmc_opp_table: dmc-opp-table { compatible = "operating-points-v2"; mbist-vmin = <825000 900000 950000>; - nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>; - nvmem-cell-names = "leakage", "pvtm", "mbist-vmin"; + nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>, <&dmc_opp_info>; + nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info"; + rockchip,max-volt = <1000000>; rockchip,temp-hysteresis = <5000>; rockchip,low-temp = <0>; rockchip,low-temp-adjust-volt = < @@ -2323,9 +2345,9 @@ dmc_opp_table: dmc-opp-table { opp-1560000000 { opp-hz = /bits/ 64 <1560000000>; - opp-microvolt = <900000>; - opp-microvolt-L0 = <900000>; - opp-microvolt-L1 = <875000>; + opp-microvolt = <900000 900000 1000000>; + opp-microvolt-L0 = <900000 900000 1000000>; + opp-microvolt-L1 = <875000 875000 1000000>; }; }; @@ -2705,6 +2727,18 @@ tsadc_trim_base_frac: tsadc-trim-base-frac@31 { tsadc_trim_base: tsadc-trim-base@32 { reg = <0x32 0x1>; }; + cpu_opp_info: cpu-opp-info@36 { + reg = <0x36 0x6>; + }; + gpu_opp_info: gpu-opp-info@3c { + reg = <0x3c 0x6>; + }; + npu_opp_info: npu-opp-info@42 { + reg = <0x42 0x6>; + }; + dmc_opp_info: dmc-opp-info@48 { + reg = <0x48 0x6>; + }; }; i2s0_8ch: i2s@fe400000 {