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phy: qcom: qmp-pcie: Add pcs_lane1 offset to V5 offsets

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Some SoCs such as SM8475 write data to registers using this offset,
specifically SW_CTRL2 and MX_CTRL2.
Add pcs_lane1 offset to V5 offsets to support this.

Signed-off-by: Esteban Urrutia <esteuwu@proton.me>
Fixes: 0fd0b31965 ("phy: qualcomm: qmp-pcie: add support for SAR2130P")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://patch.msgid.link/20260715-sm8475-bup-pcie-v2-2-48bd91a19abf@proton.me
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Esteban Urrutia 2026-07-15 02:37:47 -04:00 committed by Vinod Koul
parent bae047e912
commit f8b4493d5e
1 changed files with 1 additions and 0 deletions
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drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
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@ -4092,6 +4092,7 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = {
.pcs_misc = 0x0600,
.tx = 0x0e00,
.rx = 0x1000,
.pcs_lane1 = 0x1400,
.tx2 = 0x1600,
.rx2 = 0x1800,
};