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arm64: dts: qcom: ipq5424-rdp466: Enable QPIC SPI NAND support
Enable QPIC SPI NAND flash controller support on the IPQ5424 RDP466 reference design platform. The RDP466 board features a SPI NAND flash device connected to the QPIC controller for primary storage. This patch enables the QPIC BAM DMA controller and SPI NAND interface of QPIC, and configures the necessary pin control settings for proper operation. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> Link: https://lore.kernel.org/r/20260306113940.1654304-4-quic_mdalam@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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@ -124,13 +124,6 @@ &qusb_phy_1 {
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status = "okay";
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};
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&sdhc {
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pinctrl-0 = <&sdc_default_state>;
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pinctrl-names = "default";
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status = "okay";
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};
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&sleep_clk {
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clock-frequency = <32000>;
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};
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@ -201,26 +194,26 @@ mosi-pins {
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};
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};
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sdc_default_state: sdc-default-state {
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clk-pins {
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qpic_snand_default_state: qpic-snand-default-state {
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clock-pins {
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pins = "gpio5";
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function = "sdc_clk";
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function = "qspi_clk";
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drive-strength = <8>;
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bias-disable;
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bias-pull-down;
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};
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cmd-pins {
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cs-pins {
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pins = "gpio4";
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function = "sdc_cmd";
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function = "qspi_cs";
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drive-strength = <8>;
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bias-pull-up;
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};
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data-pins {
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pins = "gpio0", "gpio1", "gpio2", "gpio3";
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function = "sdc_data";
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function = "qspi_data";
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drive-strength = <8>;
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bias-pull-up;
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bias-pull-down;
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};
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};
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@ -246,6 +239,27 @@ pcie3_default_state: pcie3-default-state {
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};
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};
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&qpic_bam {
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status = "okay";
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};
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&qpic_nand {
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pinctrl-0 = <&qpic_snand_default_state>;
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pinctrl-names = "default";
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status = "okay";
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flash@0 {
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compatible = "spi-nand";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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nand-ecc-engine = <&qpic_nand>;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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};
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};
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&uart0 {
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pinctrl-0 = <&uart0_pins>;
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pinctrl-names = "default";
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