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PCI: cadence: Add support to build pcie-cadence library as a kernel module
Currently, the Cadence PCIe controller driver can be built as a built-in module only. Since PCIe functionality is not a necessity for booting, add support to build the Cadence PCIe driver as a loadable module as well. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://patch.msgid.link/20250417124408.2752248-2-s-vadapalli@ti.com
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@ -4,16 +4,16 @@ menu "Cadence-based PCIe controllers"
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depends on PCI
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config PCIE_CADENCE
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bool
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tristate
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config PCIE_CADENCE_HOST
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bool
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tristate
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depends on OF
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select IRQ_DOMAIN
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select PCIE_CADENCE
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config PCIE_CADENCE_EP
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bool
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tristate
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depends on OF
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depends on PCI_ENDPOINT
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select PCIE_CADENCE
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@ -6,6 +6,7 @@
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#include <linux/bitfield.h>
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/pci-epc.h>
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#include <linux/platform_device.h>
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@ -752,3 +753,8 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
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return ret;
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}
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EXPORT_SYMBOL_GPL(cdns_pcie_ep_setup);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("Cadence PCIe endpoint controller driver");
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MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@free-electrons.com>");
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@ -5,6 +5,7 @@
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/list_sort.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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@ -72,6 +73,7 @@ void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
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return rc->cfg_base + (where & 0xfff);
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}
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EXPORT_SYMBOL_GPL(cdns_pci_map_bus);
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static struct pci_ops cdns_pcie_host_ops = {
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.map_bus = cdns_pci_map_bus,
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@ -495,6 +497,7 @@ int cdns_pcie_host_init(struct cdns_pcie_rc *rc)
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return cdns_pcie_host_init_address_translation(rc);
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}
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EXPORT_SYMBOL_GPL(cdns_pcie_host_init);
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int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc)
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{
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@ -519,6 +522,7 @@ int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc)
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return 0;
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}
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EXPORT_SYMBOL_GPL(cdns_pcie_host_link_setup);
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int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
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{
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@ -572,3 +576,8 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
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return pci_host_probe(bridge);
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}
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EXPORT_SYMBOL_GPL(cdns_pcie_host_setup);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("Cadence PCIe host controller driver");
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MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@free-electrons.com>");
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@ -4,6 +4,7 @@
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// Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include "pcie-cadence.h"
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@ -23,6 +24,7 @@ void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie)
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cdns_pcie_writel(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP, ltssm_control_cap);
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}
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EXPORT_SYMBOL_GPL(cdns_pcie_detect_quiet_min_delay_set);
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void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn,
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u32 r, bool is_io,
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@ -100,6 +102,7 @@ void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn,
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r), addr0);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r), addr1);
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}
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EXPORT_SYMBOL_GPL(cdns_pcie_set_outbound_region);
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void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie,
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u8 busnr, u8 fn,
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@ -134,6 +137,7 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie,
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r), addr0);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r), addr1);
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}
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EXPORT_SYMBOL_GPL(cdns_pcie_set_outbound_region_for_normal_msg);
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void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r)
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{
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@ -146,6 +150,7 @@ void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r)
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r), 0);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r), 0);
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}
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EXPORT_SYMBOL_GPL(cdns_pcie_reset_outbound_region);
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void cdns_pcie_disable_phy(struct cdns_pcie *pcie)
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{
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@ -156,6 +161,7 @@ void cdns_pcie_disable_phy(struct cdns_pcie *pcie)
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phy_exit(pcie->phy[i]);
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}
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}
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EXPORT_SYMBOL_GPL(cdns_pcie_disable_phy);
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int cdns_pcie_enable_phy(struct cdns_pcie *pcie)
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{
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@ -184,6 +190,7 @@ int cdns_pcie_enable_phy(struct cdns_pcie *pcie)
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return ret;
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}
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EXPORT_SYMBOL_GPL(cdns_pcie_enable_phy);
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int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
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{
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@ -243,6 +250,7 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
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return ret;
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}
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EXPORT_SYMBOL_GPL(cdns_pcie_init_phy);
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static int cdns_pcie_suspend_noirq(struct device *dev)
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{
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@ -271,3 +279,7 @@ const struct dev_pm_ops cdns_pcie_pm_ops = {
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NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq,
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cdns_pcie_resume_noirq)
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};
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("Cadence PCIe controller driver");
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MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@free-electrons.com>");
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@ -508,7 +508,7 @@ static inline bool cdns_pcie_link_up(struct cdns_pcie *pcie)
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return true;
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}
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#ifdef CONFIG_PCIE_CADENCE_HOST
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#if IS_ENABLED(CONFIG_PCIE_CADENCE_HOST)
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int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc);
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int cdns_pcie_host_init(struct cdns_pcie_rc *rc);
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int cdns_pcie_host_setup(struct cdns_pcie_rc *rc);
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@ -537,7 +537,7 @@ static inline void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int d
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}
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#endif
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#ifdef CONFIG_PCIE_CADENCE_EP
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#if IS_ENABLED(CONFIG_PCIE_CADENCE_EP)
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int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep);
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#else
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static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
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