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drm/i915: move CNP clock gating init into intel_pch

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Move the CNP PCH clock gating programming into
intel_pch_init_clock_gating() and switch the corresponding
CFL/CML caller to the display-specific code.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patch.msgid.link/20260324080441.154609-5-luciano.coelho@intel.com
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
This commit is contained in:
Luca Coelho 2026-03-24 10:04:28 +02:00
parent cf37495ad1
commit f86b08bf17
2 changed files with 11 additions and 12 deletions
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10
drivers/gpu/drm/i915/display/intel_pch.c
View File

@ -279,6 +279,13 @@ static void intel_pch_lpt_init_clock_gating(struct intel_display *display)
TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
}
static void intel_pch_cnp_init_clock_gating(struct intel_display *display)
{
/* Display WA #1181 WaSouthDisplayDisablePWMCGEGating: cnp */
intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 0,
CNP_PWM_CGE_GATING_DISABLE);
}
void intel_pch_init_clock_gating(struct intel_display *display)
{
switch (INTEL_PCH_TYPE(display)) {
@ -292,6 +299,9 @@ void intel_pch_init_clock_gating(struct intel_display *display)
case PCH_LPT_LP:
intel_pch_lpt_init_clock_gating(display);
break;
case PCH_CNP:
intel_pch_cnp_init_clock_gating(display);
break;
default:
break;
}

13
drivers/gpu/drm/i915/intel_clock_gating.c
View File

@ -299,20 +299,9 @@ static void dg2_init_clock_gating(struct drm_i915_private *i915)
SGSI_SIDECLK_DIS);
}
static void cnp_init_clock_gating(struct drm_i915_private *i915)
{
struct intel_display *display = i915->display;
if (!HAS_PCH_CNP(display))
return;
/* Display WA #1181 WaSouthDisplayDisablePWMCGEGating: cnp */
intel_uncore_rmw(&i915->uncore, SOUTH_DSPCLK_GATE_D, 0, CNP_PWM_CGE_GATING_DISABLE);
}
static void cfl_init_clock_gating(struct drm_i915_private *i915)
{
cnp_init_clock_gating(i915);
intel_pch_init_clock_gating(i915->display);
gen9_init_clock_gating(i915);
/* WAC6entrylatency:cfl */