From f81bcaae1edde95c684436310edad8cf849f1f1f Mon Sep 17 00:00:00 2001 From: Ravi Hothi Date: Wed, 15 Jul 2026 18:51:49 +0530 Subject: [PATCH] dt-bindings: pinctrl: qcom,milos-lpass-lpi-pinctrl: Add Eliza pinctrl Document compatible for Qualcomm Eliza SoC LPASS LPI pin controller. Eliza has the same pin mux functions as Milos but uses a different slew rate register layout where the slew rate field is in the same GPIO config register rather than a separate dedicated register. As a result, Eliza only has a single reg entry instead of two. Signed-off-by: Ravi Hothi Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260715132150.1322663-2-ravi.hothi@oss.qualcomm.com Signed-off-by: Bartosz Golaszewski --- .../pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml index 73e84f188591..86c1da0f577c 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml @@ -15,9 +15,12 @@ description: properties: compatible: - const: qcom,milos-lpass-lpi-pinctrl + enum: + - qcom,eliza-lpass-lpi-pinctrl + - qcom,milos-lpass-lpi-pinctrl reg: + minItems: 1 items: - description: LPASS LPI TLMM Control and Status registers - description: LPASS LPI MCC registers @@ -74,6 +77,19 @@ $defs: allOf: - $ref: qcom,lpass-lpi-common.yaml# + - if: + properties: + compatible: + const: qcom,eliza-lpass-lpi-pinctrl + then: + properties: + reg: + maxItems: 1 + else: + properties: + reg: + minItems: 2 + required: - compatible - reg