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riscv, bpf: Remap BPF_REG_0 and RV_REG_TCC
To prepare for supporting bpf stack arguments and unifying the calling convention between bpf2bpf calls and kfunc calls, remap BPF_REG_0 to t6 and RV_REG_TCC to t5. In the riscv abi, a0-a7 are designated for function argument passing. Freeing a5 and a6 allows bpf2bpf calls to pass extra arguments (6th to 8th) via a5-a7 consistently with kfuncs. Signed-off-by: Pu Lehui <pulehui@huawei.com> Acked-by: Björn Töpel <bjorn@kernel.org> Link: https://lore.kernel.org/bpf/20260905085857.14143-2-pulehui@huaweicloud.com Signed-off-by: Kumar Kartikeya Dwivedi <memxor@gmail.com>
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3ccdb07813
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f80a09c486
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@ -23,11 +23,11 @@
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/* fentry and TCC init insns will be skipped on tailcall */
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#define RV_TAILCALL_OFFSET ((RV_FENTRY_NINSNS + 1) * 4)
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#define RV_REG_TCC RV_REG_A6
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#define RV_REG_TCC RV_REG_T5
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#define RV_REG_ARENA RV_REG_S7 /* For storing arena_vm_start */
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static const int regmap[] = {
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[BPF_REG_0] = RV_REG_A5,
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[BPF_REG_0] = RV_REG_T6,
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[BPF_REG_1] = RV_REG_A0,
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[BPF_REG_2] = RV_REG_A1,
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[BPF_REG_3] = RV_REG_A2,
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@ -47,13 +47,13 @@ static const int pt_regmap[] = {
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[RV_REG_A2] = offsetof(struct pt_regs, a2),
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[RV_REG_A3] = offsetof(struct pt_regs, a3),
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[RV_REG_A4] = offsetof(struct pt_regs, a4),
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[RV_REG_A5] = offsetof(struct pt_regs, a5),
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[RV_REG_S1] = offsetof(struct pt_regs, s1),
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[RV_REG_S2] = offsetof(struct pt_regs, s2),
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[RV_REG_S3] = offsetof(struct pt_regs, s3),
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[RV_REG_S4] = offsetof(struct pt_regs, s4),
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[RV_REG_S5] = offsetof(struct pt_regs, s5),
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[RV_REG_T0] = offsetof(struct pt_regs, t0),
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[RV_REG_T6] = offsetof(struct pt_regs, t6),
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};
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enum {
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@ -239,7 +239,7 @@ static void __build_epilogue(bool is_tail_call, struct rv_jit_context *ctx)
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emit_addi(RV_REG_SP, RV_REG_SP, stack_adjust, ctx);
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/* Set return value. */
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if (!is_tail_call)
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emit_addiw(RV_REG_A0, RV_REG_A5, 0, ctx);
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emit_addiw(RV_REG_A0, regmap[BPF_REG_0], 0, ctx);
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emit_jalr(RV_REG_ZERO, is_tail_call ? RV_REG_T3 : RV_REG_RA,
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is_tail_call ? RV_TAILCALL_OFFSET : 0, ctx);
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}
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@ -1075,7 +1075,7 @@ static int __arch_prepare_bpf_trampoline(struct bpf_tramp_image *im,
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save_ret = flags & (BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_RET_FENTRY_RET);
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if (save_ret)
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stack_size += 16; /* Save both A5 (BPF R0) and A0 */
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stack_size += 16; /* Save both RV_REG_T6 (BPF R0) and RV_REG_A0 */
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retval_off = stack_size;
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stack_size += nr_arg_slots * 8;
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@ -10,7 +10,7 @@
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* - output: updated count in BPF_REG_AX (t0)
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*
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* Calls bpf_check_timed_may_goto(ptr) with the standard RISC-V ABI, where
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* ptr = BPF_REG_FP (s5) + BPF_REG_AX (t0). BPF R0-R5 (a5, a0-a4) are saved
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* ptr = BPF_REG_FP (s5) + BPF_REG_AX (t0). BPF R0-R5 (t6, a0-a4) are saved
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* across the call; BPF_REG_FP (s5) is callee-saved and needs no saving.
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*/
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@ -20,8 +20,8 @@ SYM_FUNC_START(arch_bpf_timed_may_goto)
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REG_S s0, 6*SZREG(sp)
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addi s0, sp, 8*SZREG
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/* Save BPF registers R0-R5 (a5, a0-a4) */
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REG_S a5, 5*SZREG(sp)
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/* Save BPF registers R0-R5 (t6, a0-a4) */
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REG_S t6, 5*SZREG(sp)
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REG_S a0, 4*SZREG(sp)
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REG_S a1, 3*SZREG(sp)
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REG_S a2, 2*SZREG(sp)
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@ -38,7 +38,7 @@ SYM_FUNC_START(arch_bpf_timed_may_goto)
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REG_L a2, 2*SZREG(sp)
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REG_L a1, 3*SZREG(sp)
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REG_L a0, 4*SZREG(sp)
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REG_L a5, 5*SZREG(sp)
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REG_L t6, 5*SZREG(sp)
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REG_L s0, 6*SZREG(sp)
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REG_L ra, 7*SZREG(sp)
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@ -11,7 +11,7 @@ __jited(" addq %gs:{{.*}}, %rax")
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__arch_arm64
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__jited(" mrs x8, SP_EL0")
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__arch_riscv64
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__jited(" mv a5, tp")
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__jited(" mv t6, tp")
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__arch_loongarch
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__jited(" move $a5, $tp")
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int inline_bpf_get_current_task(void)
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@ -289,11 +289,11 @@ __jited("ldrsh x22, [x11, #0x18]")
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__jited("add x11, x0, x28")
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__jited("ldrsb x22, [x11, #0x20]")
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__arch_riscv64
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__jited("add t2, a5, s7")
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__jited("add t2, t6, s7")
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__jited("lw s3, 0x10(t2)")
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__jited("add t2, a5, s7")
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__jited("add t2, t6, s7")
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__jited("lh s3, 0x18(t2)")
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__jited("add t2, a5, s7")
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__jited("add t2, t6, s7")
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__jited("lb s3, 0x20(t2)")
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__jited("add t2, a0, s7")
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__jited("lw s4, 0x10(t2)")
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