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net: stmmac: rk: add GMAC_CLK_xx constants, simplify RGMII definitions
All the definitions of the RGMII related xxx_GMAC_CLK_xxx definitions use the same field values to select the clock rate. Provide common definitions for these field values, passing them in to a single macro for each variant that generates the appropriate values for the speed register. No change to produced code on aarch64. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Link: https://patch.msgid.link/E1vl3G0-00000006v3R-2ZBc@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Russell King (Oracle)
Jakub Kicinski
parent
1c249fc1e1
commit
f7aaa6fb11
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@ -91,6 +91,10 @@ struct rk_priv_data {
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struct regmap *php_grf;
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};
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#define GMAC_CLK_DIV1_125M 0
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#define GMAC_CLK_DIV50_2_5M 2
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#define GMAC_CLK_DIV5_25M 3
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static int rk_set_reg_speed(struct rk_priv_data *bsp_priv,
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const struct rk_reg_speed_data *rsd,
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unsigned int reg, phy_interface_t interface,
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@ -299,9 +303,7 @@ static const struct rk_gmac_ops px30_ops = {
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#define RK3128_GMAC_SPEED_100M GRF_BIT(10)
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#define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11)
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#define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
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#define RK3128_GMAC_CLK_125M GRF_FIELD_CONST(13, 12, 0)
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#define RK3128_GMAC_CLK_25M GRF_FIELD_CONST(13, 12, 3)
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#define RK3128_GMAC_CLK_2_5M GRF_FIELD_CONST(13, 12, 2)
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#define RK3128_GMAC_CLK(val) GRF_FIELD_CONST(13, 12, val)
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#define RK3128_GMAC_RMII_MODE GRF_BIT(14)
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#define RK3128_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
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@ -325,9 +327,9 @@ static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
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}
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static const struct rk_reg_speed_data rk3128_reg_speed_data = {
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.rgmii_10 = RK3128_GMAC_CLK_2_5M,
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.rgmii_100 = RK3128_GMAC_CLK_25M,
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.rgmii_1000 = RK3128_GMAC_CLK_125M,
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.rgmii_10 = RK3128_GMAC_CLK(GMAC_CLK_DIV50_2_5M),
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.rgmii_100 = RK3128_GMAC_CLK(GMAC_CLK_DIV5_25M),
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.rgmii_1000 = RK3128_GMAC_CLK(GMAC_CLK_DIV1_125M),
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.rmii_10 = RK3128_GMAC_RMII_CLK_2_5M | RK3128_GMAC_SPEED_10M,
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.rmii_100 = RK3128_GMAC_RMII_CLK_25M | RK3128_GMAC_SPEED_100M,
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};
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@ -362,9 +364,7 @@ static const struct rk_gmac_ops rk3128_ops = {
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#define RK3228_GMAC_SPEED_100M GRF_BIT(2)
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#define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7)
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#define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
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#define RK3228_GMAC_CLK_125M GRF_FIELD_CONST(9, 8, 0)
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#define RK3228_GMAC_CLK_25M GRF_FIELD_CONST(9, 8, 3)
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#define RK3228_GMAC_CLK_2_5M GRF_FIELD_CONST(9, 8, 2)
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#define RK3228_GMAC_CLK(val) GRF_FIELD_CONST(9, 8, val)
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#define RK3228_GMAC_RMII_MODE GRF_BIT(10)
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#define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10)
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#define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
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@ -399,9 +399,9 @@ static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
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}
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static const struct rk_reg_speed_data rk3228_reg_speed_data = {
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.rgmii_10 = RK3228_GMAC_CLK_2_5M,
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.rgmii_100 = RK3228_GMAC_CLK_25M,
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.rgmii_1000 = RK3228_GMAC_CLK_125M,
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.rgmii_10 = RK3228_GMAC_CLK(GMAC_CLK_DIV50_2_5M),
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.rgmii_100 = RK3228_GMAC_CLK(GMAC_CLK_DIV5_25M),
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.rgmii_1000 = RK3228_GMAC_CLK(GMAC_CLK_DIV1_125M),
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.rmii_10 = RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_SPEED_10M,
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.rmii_100 = RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_SPEED_100M,
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};
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@ -440,9 +440,7 @@ static const struct rk_gmac_ops rk3228_ops = {
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#define RK3288_GMAC_SPEED_100M GRF_BIT(10)
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#define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11)
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#define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
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#define RK3288_GMAC_CLK_125M GRF_FIELD_CONST(13, 12, 0)
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#define RK3288_GMAC_CLK_25M GRF_FIELD_CONST(13, 12, 3)
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#define RK3288_GMAC_CLK_2_5M GRF_FIELD_CONST(13, 12, 2)
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#define RK3288_GMAC_CLK(val) GRF_FIELD_CONST(13, 12, val)
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#define RK3288_GMAC_RMII_MODE GRF_BIT(14)
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#define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
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@ -474,9 +472,9 @@ static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
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}
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static const struct rk_reg_speed_data rk3288_reg_speed_data = {
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.rgmii_10 = RK3288_GMAC_CLK_2_5M,
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.rgmii_100 = RK3288_GMAC_CLK_25M,
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.rgmii_1000 = RK3288_GMAC_CLK_125M,
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.rgmii_10 = RK3288_GMAC_CLK(GMAC_CLK_DIV50_2_5M),
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.rgmii_100 = RK3288_GMAC_CLK(GMAC_CLK_DIV5_25M),
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.rgmii_1000 = RK3288_GMAC_CLK(GMAC_CLK_DIV1_125M),
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.rmii_10 = RK3288_GMAC_RMII_CLK_2_5M | RK3288_GMAC_SPEED_10M,
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.rmii_100 = RK3288_GMAC_RMII_CLK_25M | RK3288_GMAC_SPEED_100M,
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};
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@ -543,9 +541,7 @@ static const struct rk_gmac_ops rk3308_ops = {
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#define RK3328_GMAC_SPEED_100M GRF_BIT(2)
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#define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7)
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#define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
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#define RK3328_GMAC_CLK_125M GRF_FIELD_CONST(12, 11, 0)
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#define RK3328_GMAC_CLK_25M GRF_FIELD_CONST(12, 11, 3)
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#define RK3328_GMAC_CLK_2_5M GRF_FIELD_CONST(12, 11, 2)
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#define RK3328_GMAC_CLK(val) GRF_FIELD_CONST(12, 11, val)
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#define RK3328_GMAC_RMII_MODE GRF_BIT(9)
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#define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9)
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#define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
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@ -580,9 +576,9 @@ static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
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}
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static const struct rk_reg_speed_data rk3328_reg_speed_data = {
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.rgmii_10 = RK3328_GMAC_CLK_2_5M,
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.rgmii_100 = RK3328_GMAC_CLK_25M,
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.rgmii_1000 = RK3328_GMAC_CLK_125M,
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.rgmii_10 = RK3328_GMAC_CLK(GMAC_CLK_DIV50_2_5M),
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.rgmii_100 = RK3328_GMAC_CLK(GMAC_CLK_DIV5_25M),
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.rgmii_1000 = RK3328_GMAC_CLK(GMAC_CLK_DIV1_125M),
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.rmii_10 = RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_SPEED_10M,
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.rmii_100 = RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_SPEED_100M,
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};
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@ -632,9 +628,7 @@ static const struct rk_gmac_ops rk3328_ops = {
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#define RK3366_GMAC_SPEED_100M GRF_BIT(7)
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#define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3)
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#define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
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#define RK3366_GMAC_CLK_125M GRF_FIELD_CONST(5, 4, 0)
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#define RK3366_GMAC_CLK_25M GRF_FIELD_CONST(5, 4, 3)
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#define RK3366_GMAC_CLK_2_5M GRF_FIELD_CONST(5, 4, 2)
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#define RK3366_GMAC_CLK(val) GRF_FIELD_CONST(5, 4, val)
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#define RK3366_GMAC_RMII_MODE GRF_BIT(6)
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#define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
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@ -666,9 +660,9 @@ static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
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}
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static const struct rk_reg_speed_data rk3366_reg_speed_data = {
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.rgmii_10 = RK3366_GMAC_CLK_2_5M,
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.rgmii_100 = RK3366_GMAC_CLK_25M,
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.rgmii_1000 = RK3366_GMAC_CLK_125M,
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.rgmii_10 = RK3366_GMAC_CLK(GMAC_CLK_DIV50_2_5M),
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.rgmii_100 = RK3366_GMAC_CLK(GMAC_CLK_DIV5_25M),
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.rgmii_1000 = RK3366_GMAC_CLK(GMAC_CLK_DIV1_125M),
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.rmii_10 = RK3366_GMAC_RMII_CLK_2_5M | RK3366_GMAC_SPEED_10M,
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.rmii_100 = RK3366_GMAC_RMII_CLK_25M | RK3366_GMAC_SPEED_100M,
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};
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@ -697,9 +691,7 @@ static const struct rk_gmac_ops rk3366_ops = {
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#define RK3368_GMAC_SPEED_100M GRF_BIT(7)
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#define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3)
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#define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
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#define RK3368_GMAC_CLK_125M GRF_FIELD_CONST(5, 4, 0)
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#define RK3368_GMAC_CLK_25M GRF_FIELD_CONST(5, 4, 3)
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#define RK3368_GMAC_CLK_2_5M GRF_FIELD_CONST(5, 4, 2)
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#define RK3368_GMAC_CLK(val) GRF_FIELD_CONST(5, 4, val)
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#define RK3368_GMAC_RMII_MODE GRF_BIT(6)
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#define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
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@ -731,9 +723,9 @@ static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
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}
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static const struct rk_reg_speed_data rk3368_reg_speed_data = {
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.rgmii_10 = RK3368_GMAC_CLK_2_5M,
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.rgmii_100 = RK3368_GMAC_CLK_25M,
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.rgmii_1000 = RK3368_GMAC_CLK_125M,
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.rgmii_10 = RK3368_GMAC_CLK(GMAC_CLK_DIV50_2_5M),
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.rgmii_100 = RK3368_GMAC_CLK(GMAC_CLK_DIV5_25M),
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.rgmii_1000 = RK3368_GMAC_CLK(GMAC_CLK_DIV1_125M),
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.rmii_10 = RK3368_GMAC_RMII_CLK_2_5M | RK3368_GMAC_SPEED_10M,
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.rmii_100 = RK3368_GMAC_RMII_CLK_25M | RK3368_GMAC_SPEED_100M,
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};
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@ -762,9 +754,7 @@ static const struct rk_gmac_ops rk3368_ops = {
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#define RK3399_GMAC_SPEED_100M GRF_BIT(7)
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#define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3)
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#define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
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#define RK3399_GMAC_CLK_125M GRF_FIELD_CONST(5, 4, 0)
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#define RK3399_GMAC_CLK_25M GRF_FIELD_CONST(5, 4, 3)
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#define RK3399_GMAC_CLK_2_5M GRF_FIELD_CONST(5, 4, 2)
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#define RK3399_GMAC_CLK(val) GRF_FIELD_CONST(5, 4, val)
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#define RK3399_GMAC_RMII_MODE GRF_BIT(6)
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#define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
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@ -796,9 +786,9 @@ static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
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}
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static const struct rk_reg_speed_data rk3399_reg_speed_data = {
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.rgmii_10 = RK3399_GMAC_CLK_2_5M,
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.rgmii_100 = RK3399_GMAC_CLK_25M,
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.rgmii_1000 = RK3399_GMAC_CLK_125M,
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.rgmii_10 = RK3399_GMAC_CLK(GMAC_CLK_DIV50_2_5M),
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.rgmii_100 = RK3399_GMAC_CLK(GMAC_CLK_DIV5_25M),
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.rgmii_1000 = RK3399_GMAC_CLK(GMAC_CLK_DIV1_125M),
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.rmii_10 = RK3399_GMAC_RMII_CLK_2_5M | RK3399_GMAC_SPEED_10M,
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.rmii_100 = RK3399_GMAC_RMII_CLK_25M | RK3399_GMAC_SPEED_100M,
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};
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@ -905,9 +895,7 @@ static const struct rk_gmac_ops rk3506_ops = {
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#define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10)
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#define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10)
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#define RK3528_GMAC1_CLK_RGMII_DIV1 GRF_FIELD_CONST(11, 10, 0)
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#define RK3528_GMAC1_CLK_RGMII_DIV5 GRF_FIELD_CONST(11, 10, 3)
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#define RK3528_GMAC1_CLK_RGMII_DIV50 GRF_FIELD_CONST(11, 10, 2)
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#define RK3528_GMAC1_CLK_RGMII(val) GRF_FIELD_CONST(11, 10, val)
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#define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2)
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#define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2)
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@ -945,9 +933,9 @@ static const struct rk_reg_speed_data rk3528_gmac0_reg_speed_data = {
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};
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static const struct rk_reg_speed_data rk3528_gmac1_reg_speed_data = {
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.rgmii_10 = RK3528_GMAC1_CLK_RGMII_DIV50,
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.rgmii_100 = RK3528_GMAC1_CLK_RGMII_DIV5,
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.rgmii_1000 = RK3528_GMAC1_CLK_RGMII_DIV1,
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.rgmii_10 = RK3528_GMAC1_CLK_RGMII(GMAC_CLK_DIV50_2_5M),
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.rgmii_100 = RK3528_GMAC1_CLK_RGMII(GMAC_CLK_DIV5_25M),
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.rgmii_1000 = RK3528_GMAC1_CLK_RGMII(GMAC_CLK_DIV1_125M),
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.rmii_10 = RK3528_GMAC1_CLK_RMII_DIV20,
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.rmii_100 = RK3528_GMAC1_CLK_RMII_DIV2,
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};
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@ -1099,9 +1087,7 @@ static const struct rk_gmac_ops rk3568_ops = {
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#define RK3576_GMAC_CLK_RMII_DIV2 GRF_BIT(5)
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#define RK3576_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(5)
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#define RK3576_GMAC_CLK_RGMII_DIV1 GRF_FIELD_CONST(6, 5, 0)
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#define RK3576_GMAC_CLK_RGMII_DIV5 GRF_FIELD_CONST(6, 5, 3)
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#define RK3576_GMAC_CLK_RGMII_DIV50 GRF_FIELD_CONST(6, 5, 2)
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#define RK3576_GMAC_CLK_RGMII(val) GRF_FIELD_CONST(6, 5, val)
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#define RK3576_GMAC_CLK_RMII_GATE GRF_BIT(4)
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#define RK3576_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(4)
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@ -1145,9 +1131,9 @@ static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv)
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}
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static const struct rk_reg_speed_data rk3578_reg_speed_data = {
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.rgmii_10 = RK3576_GMAC_CLK_RGMII_DIV50,
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.rgmii_100 = RK3576_GMAC_CLK_RGMII_DIV5,
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.rgmii_1000 = RK3576_GMAC_CLK_RGMII_DIV1,
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.rgmii_10 = RK3576_GMAC_CLK_RGMII(GMAC_CLK_DIV50_2_5M),
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.rgmii_100 = RK3576_GMAC_CLK_RGMII(GMAC_CLK_DIV5_25M),
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.rgmii_1000 = RK3576_GMAC_CLK_RGMII(GMAC_CLK_DIV1_125M),
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.rmii_10 = RK3576_GMAC_CLK_RMII_DIV20,
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.rmii_100 = RK3576_GMAC_CLK_RMII_DIV2,
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};
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@ -1223,12 +1209,8 @@ static const struct rk_gmac_ops rk3576_ops = {
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#define RK3588_GMA_CLK_RMII_DIV2(id) GRF_BIT(5 * (id) + 2)
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#define RK3588_GMA_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2)
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#define RK3588_GMAC_CLK_RGMII_DIV1(id) \
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(GRF_FIELD_CONST(3, 2, 0) << ((id) * 5))
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#define RK3588_GMAC_CLK_RGMII_DIV5(id) \
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(GRF_FIELD_CONST(3, 2, 3) << ((id) * 5))
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#define RK3588_GMAC_CLK_RGMII_DIV50(id) \
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(GRF_FIELD_CONST(3, 2, 2) << ((id) * 5))
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#define RK3588_GMAC_CLK_RGMII(id, val) \
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(GRF_FIELD_CONST(3, 2, val) << ((id) * 5))
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#define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1)
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#define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1)
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@ -1275,17 +1257,17 @@ static int rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv,
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if (interface == PHY_INTERFACE_MODE_RMII)
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val = RK3588_GMA_CLK_RMII_DIV20(id);
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else
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val = RK3588_GMAC_CLK_RGMII_DIV50(id);
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val = RK3588_GMAC_CLK_RGMII(id, GMAC_CLK_DIV50_2_5M);
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break;
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case 100:
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if (interface == PHY_INTERFACE_MODE_RMII)
|
||||
val = RK3588_GMA_CLK_RMII_DIV2(id);
|
||||
else
|
||||
val = RK3588_GMAC_CLK_RGMII_DIV5(id);
|
||||
val = RK3588_GMAC_CLK_RGMII(id, GMAC_CLK_DIV5_25M);
|
||||
break;
|
||||
case 1000:
|
||||
if (interface != PHY_INTERFACE_MODE_RMII)
|
||||
val = RK3588_GMAC_CLK_RGMII_DIV1(id);
|
||||
val = RK3588_GMAC_CLK_RGMII(id, GMAC_CLK_DIV1_125M);
|
||||
else
|
||||
goto err;
|
||||
break;
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user