From f79070bcf817a63603203629b55f92dd341e1260 Mon Sep 17 00:00:00 2001
From: Chris Goldsworthy <quic_cgoldswo@quicinc.com>
Date: Wed, 27 Apr 2022 19:21:47 -0700
Subject: [PATCH] qcom-dma-mapping: Take a snapshot of qcom-dma-mapping.h from
 msm-5.15

Take a snapshot of the qcom-dma-mapping.h header as of commit
f843a80d2c45 ("Merge "defconfig: gen3auto: Separated if_changed"") on
msm-5.15.  Additionally, add the stubbed versions of the
DMA_ATTR_SYS_CACHE_ONLY and DMA_ATTR_SYS_CACHE_ONLY_NWA attributes, as
these are yet to be merged upstream.

Change-Id: I3267f809622239ff13f0599d3a32c00b1dbf9f30
Signed-off-by: Chris Goldsworthy <quic_cgoldswo@quicinc.com>
---
 include/linux/qcom-dma-mapping.h | 47 ++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 include/linux/qcom-dma-mapping.h

diff --git a/include/linux/qcom-dma-mapping.h b/include/linux/qcom-dma-mapping.h
new file mode 100644
index 000000000000..32c14d19ae6a
--- /dev/null
+++ b/include/linux/qcom-dma-mapping.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ */
+
+/*
+ * DMA_ATTR_NO_DELAYED_UNMAP: Used by msm specific lazy mapping to indicate
+ * that the mapping can be freed on unmap, rather than when the ion_buffer
+ * is freed.
+ */
+#define DMA_ATTR_NO_DELAYED_UNMAP	(1UL << 13)
+/*
+ * When passed to a DMA map call the DMA_ATTR_FORCE_COHERENT DMA
+ * attribute can be used to force a buffer to be mapped as IO coherent.
+ */
+#define DMA_ATTR_FORCE_COHERENT			(1UL << 15)
+/*
+ * When passed to a DMA map call the DMA_ATTR_FORCE_NON_COHERENT DMA
+ * attribute can be used to force a buffer to not be mapped as IO
+ * coherent.
+ */
+#define DMA_ATTR_FORCE_NON_COHERENT		(1UL << 16)
+/*
+ * DMA_ATTR_DELAYED_UNMAP: Used by ION, it will ensure that mappings are not
+ * removed on unmap but instead are removed when the ion_buffer is freed.
+ */
+#define DMA_ATTR_DELAYED_UNMAP		(1UL << 17)
+
+#ifndef DMA_ATTR_SYS_CACHE_ONLY
+/* Attributes are not supported, so render them ineffective. */
+#define DMA_ATTR_SYS_CACHE_ONLY		(0UL)
+#define DMA_ATTR_SYS_CACHE_ONLY_NWA	(0UL)
+#endif
+
+/*
+ * DMA_ATTR_IOMMU_USE_UPSTREAM_HINT: Normally an smmu will override any bus
+ * attributes (i.e cacheablilty) provided by the client device. Some hardware
+ * may be designed to use the original attributes instead.
+ */
+#define DMA_ATTR_IOMMU_USE_UPSTREAM_HINT	(DMA_ATTR_SYS_CACHE_ONLY)
+
+/*
+ * DMA_ATTR_IOMMU_USE_LLC_NWA: Overrides the bus attributes to use the System
+ * Cache(LLC) with allocation policy as Inner Non-Cacheable, Outer Cacheable:
+ * Write-Back, Read-Allocate, No Write-Allocate policy.
+ */
+#define DMA_ATTR_IOMMU_USE_LLC_NWA	(DMA_ATTR_SYS_CACHE_ONLY_NWA)